View MC68HC08AZ32_279931.PDF datasheet online --- IC-ON-LINE

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MC68HC08AZ32/D
MC68HC08AZ32
Advance Information
January 31, 2000
List of Sections List of Sections
List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 51 System Integration Module (SIM). . . . . . . . . . . . . . . . . . 69 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . 91 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Break Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Computer Operating Properly Module (COP) . . . . . . 143 Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . 149
(c) Motorola, Inc., 2000 MOTOROLA List of Sections
MC68HC08AZ32 1
List of Sections External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . 155 Serial Communications Interface Module (SCI). . . . . 163 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . 197 Timer Interface Module A (TIMA) . . . . . . . . . . . . . . . . . 231 Timer Interface Module B (TIMB) . . . . . . . . . . . . . . . . . 257 Programmable Interrupt Timer (PIT) . . . . . . . . . . . . . . . 279 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . 287 Keyboard Module (KB) . . . . . . . . . . . . . . . . . . . . . . . . . 299 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 msCAN08 Controller (msCAN08) . . . . . . . . . . . . . . . . . 331 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Appendix A: Future EEPROM Registers . . . . . . . . . . . . 391 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
MC68HC08AZ32 2 List of Sections MOTOROLA
Table of Contents Table of Contents
List of Sections Table of Contents General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I/O section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
MC68HC08AZ32 MOTOROLA Table of Contents 3
Memory Map
RAM
ROM
EEPROM
Central Processor Unit (CPU)
Table of Contents
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 SIM bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . .72 Reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 SIM counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 SIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 CGM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 CGM during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . .114 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Clock Generator Module (CGM)
Mask Options
Break Module
Monitor ROM (MON)
MC68HC08AZ32 4 Table of Contents MOTOROLA
Table of Contents
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Computer Operating Properly Module (COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 143 144 146 147 147 147 148 148 149 149 150 150 152 153 153 155 155 155 156 160 160 163 163 164 165 179 180 180 181
Low-Voltage Inhibit (LVI)
External Interrupt Module (IRQ)
Serial Communications Interface Module (SCI)
Serial Peripheral Interface Module (SPI)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MC68HC08AZ32 MOTOROLA Table of Contents 5
Table of Contents
Pin name conventions and I/O register addresses . . . . . . . . . . . . . .199 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 Queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 SPI during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Timer Interface Module A (TIMA) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 TIMA during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 TIMB during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 PIT during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Timer Interface Module B (TIMB)
Programmable Interrupt Timer (PIT)
MC68HC08AZ32 6 Table of Contents MOTOROLA
Table of Contents
Analog-to-Digital Converter (ADC)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
287 288 288 289 291 292 293 294 299 299 299 300 303 305 307 308 309 311 314 317 320 324 327 329 331 332 333 334 335 340 341 346 347 350 351 354
Keyboard Module (KB)
I/O Ports
msCAN08 Controller (msCAN08)
MC68HC08AZ32 MOTOROLA Table of Contents 7
Table of Contents
Programmer's model of message storage . . . . . . . . . . . . . . . . . . . .355 Programmer's model of control registers . . . . . . . . . . . . . . . . . . . . .360 Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .380 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 5.0 vdc 0.5v Serial Peripheral Interface (SPI) Timing . . . . . . . . . .383 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . . .387 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 EEPROM Timebase Divider Control Registers . . . . . . . . . . . . . . . .391 EEDIVH and EEDIVL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 EEDIV Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Appendix A: Future EEPROM Registers
Glossary Index Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418 Motorola SPS World Marketing World Wide Web Server . . . . . . . . .418 Microcontroller Division's Web Site . . . . . . . . . . . . . . . . . . . . . . . . .418
MC68HC08AZ32 8 Table of Contents MOTOROLA
General Description
General Description
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply pins (Vdd and Vss) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Oscillator pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . 15 External reset pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External interrupt pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog power supply pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog ground pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog ground pin (AVSS/VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . 15 ADC voltage reference pin (VREFH) . . . . . . . . . . . . . . . . . . . . . . . 15 Analog supply pin (VDDAREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Port A input/output (I/O) pins (PTA7-PTA0) . . . . . . . . . . . . . . . . . . 16 Port B I/O pins (PTB7/ATD7-PTB0/ATD0). . . . . . . . . . . . . . . . . . . 16 Port C I/O pins (PTC5-PTC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port D I/O pins (PTD7-PTD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port E I/O pins (PTE7/SPSCK-PTE0/TxD) . . . . . . . . . . . . . . . . . . 16 Port F I/O pins (PTF6-PTF0/TACH2) . . . . . . . . . . . . . . . . . . . . . . . 16 Port G I/O pins (PTG2/KBD2-PTG0/KBD0) . . . . . . . . . . . . . . . . . . 17 Port H I/O pins (PTH1/KBD4-PTH0/KBD3) . . . . . . . . . . . . . . . . . . 17 CAN transmit pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CAN receive pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
NOTE:
This document should not be used for the MC68HC08AZ48 or MC68HC08AZ60. These devices have different functionality including a different register set and thus are covered in a separate document, MC68HC08AZ60/D.
1-gen
MC68HC08AZ32 General Description 9
MOTOROLA
General Description
Introduction
The MC68HC08AZ32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Features
Features of the MC68HC08AZ32 include the following: * * * * * * * * * * * * * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 families 8.4MHz internal bus frequency at 125C msCAN Controller (Motorola Scalable CAN) (implementing CAN 2.0b protocol as defined in BOSCH specification Sep. 1991) Available in 64 QFP package 32,272 bytes User ROM User ROM data security 512 bytes of on-chip EEPROM with security feature 1K byte of on-chip RAM Serial Peripheral Interface (SPI) module Serial Communications Interface (SCI) module 16-bit timer interface module (TIMA) with four input capture/output compare channels 16-bit timer interface module (TIMB) with two input capture/output compare channels Periodic Interrupt Timer (PIT)
MC68HC08AZ32 10 General Description
2-gen
MOTOROLA
General Description Features
* * * *
Clock Generator Module (CGM) 8-bit, 8- or 15-channel Analog to Digital Convertor module (ADC) 5-bit key wakeup port System protection features - Optional Computer Operating Properly (COP) reset - Low-voltage detection with optional reset - Illegal opcode detection with optional reset - Illegal address detection with optional reset
* *
Low-power design (fully static with STOP and WAIT modes) Master reset pin and power-on reset
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (8 more than the HC05) 16-Bit Index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-Coded Decimal (BCD) instructions Optimization for controller applications `C' language support
Figure 1 shows the structure of the MC68HC08AZ32
3-gen
MC68HC08AZ32 General Description 11
MOTOROLA
.
CPU REGISTERS
ARITHMETIC/LOGIC UNIT (ALU)
SERIAL COMMUNICATIONS INTERFACE MODULE CANRx CANTx msCAN CONTROLLER MODULE BREAK MODULE LOW VOLTAGE INHIBIT MODULE
PTA
M68HC08 CPU
DDRA
DDRB
PTB
DDRC
USER RAM -- 1024 BYTES USER EEPROM -- 512 BYTES
PTC
DDRD
USER ROM -- 32,255 BYTES MONITOR ROM -- 224 BYTES USER ROM VECTOR SPACE -- 48BYTES OSC1 OSC2 CGMXFC RST CLOCK GENERATOR MODULE COMPUTER OPERATING PROPERLY MODULE TIMER1 & 2 INTERFACE MODULES (4 + 2 Channels)
PTD
DDRE
SERIAL PERIPHERAL INTERFACE MODULE ANALOG TO DIGITAL CONVERTOR MODULE
SYSTEM INTEGRATION MODULE IRQ MODULE POWER-ON RESET MODULE
PTE
DDRF
PROGRAMMABLE INTERRUPT TIMER MODULE KEYBOARD INTERRUPT MODULE
DDRG
PTG
PTF
POWER
PTH
VSSA VDDA
DDRH
12 General Description MOTOROLA
MC68HC08AZ32
IRQ 4-gen
General Description
PTA7-PTA0
PTB7/ATD7-PTB0/ATD0
CONTROL AND STATUS REGISTERS
PTC5-PTC3 PTC2/MCLK PTC1-PTC0 PTD7 PTD6/ATD14/TACLK PTD5/ATD13/ATD13 PTD4/ATD12/TBCLK PTD3/ATD11/ATD11 PTD2/ATD10/ATD10 PTD1/ATD9/ATD9PTD0/ATD8/ATD8 PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1-PTF4/TBCH0 PTF3/TACH5-PTF2/TACH4 PTF1/TACH3 PTF0/TACH2
PTG2/KBD2-PTG0/KBD0
VDD VSS
VREFH AVSS/VREVDDAREF EVSS4-EVSS1 EVDD3-EVDD1
PTH1/KBD4-PTH0/KBD3
Figure 1. MC68HC08AZ32 MCU block diagram
General Description Pin Assignments
Pin Assignments
Figure 2 shows the 64 QFP pin assignments.
PTD6/ATD14/TACLK
PTD4/ATD12/TBLCK 50
PTD5/ATD13
PTC2/MCLK
64
63
62
61
60
59
58
57
56
55
54
53
52
PTC4 IRQ RST PTF0/TACH2 PTF1/TACH3 PTF2 PTF3 PTF4/TBCH0 CANRx CANTx PTF5/TBCH1 PTF6 PTE0/TxD PTE1/RxD PTE2/TACH0
51
49
PTH1/KBD4
CGMXFC
VREFH
OSC1
OSC2
PTC5
PTC3
PTC1
PTC0
PTD7
VSSA
vDDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
PTH0/KBD3 PTD3/ATD11 PTD2/ATD10 AVSS/VREFL VDDAREF PTD1/ATD9 PTD0/ATD8 PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0
MC68HC08AZ32
41 40 39 38 37 36 35 34
18
19
20
21
22
23
24
25
26
27
28
29
30
PTE4/SS 17
31
PTE3/TACH1 16
33 PTA6 32
PTA7
PTE5/MISO
PTE6/MOSI
VSS
PTG0/KBD0
PTG1/KBD1
PTE7/SPSCK
PTG2/KBD2
PTA0
PTA1
PTA2
PTA3
PTA4
Figure 2. 64 QFP pin assignments
PTA5
VDD
5-gen
MC68HC08AZ32 General Description 13
MOTOROLA
General Description
Power supply pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 3. shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
MCU
VDD VSS
C1 0.1 F + C2
VDD
NOTE: Component values shown represent typical applications.
Figure 3.Power supply bypassing VSS is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (SPI).
NOTE:
VSS must be grounded for proper MCU operation.
MC68HC08AZ32 14 General Description
6-gen
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General Description Pin Assignments
Oscillator pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Clock Generator Module (CGM) on page 91.
External reset pin (RST)
A `0' on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See System Integration Module (SIM) on page 69.
External interrupt pin (IRQ)
IRQ is an asynchronous external interrupt pin. See External Interrupt Module (IRQ) on page 155.
Analog power supply pin (VDDA)
VDDA is the power supply pin for the clock generator module (CGM).
Analog ground pin (VSSA)
The VSSA analog ground pin is used only for the ground connections for the clock generator module (CGM) section of the circuit and should be decoupled as per the VSS digital ground pin. See Clock Generator Module (CGM) on page 91.
Analog ground pin (AVSS/VREFL)
The AVSS analog ground pin is used only for the ground connections for the analog to digital convertor (ADC) and should be decoupled as per the VSS digital ground pin.
ADC voltage reference pin (VREFH)
VREFH is the power supply for setting the reference voltage VREFH. Connect the VREFH pin to a voltage potential<= VDDAREF, not less than 1.5V.
Analog supply pin (VDDAREF)
The VDDAREF analog supply pin is used only for the supply connections for the analog to digital convertor (ADC).External filter capacitor pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Clock Generator Module (CGM) on page 91.
7-gen
MC68HC08AZ32 General Description 15
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General Description
Port A input/output (I/O) pins (PTA7-PTA0) PTA7-PTA0 are general-purpose bidirectional I/O port pins. See I/O Ports on page 307.
Port B I/O pins (PTB7/ATD7PTB0/ ATD0)
Port B is an 8-bit special function port that shares all eight pins with the analog to digital convertor (ADC). See Analog-to-Digital Converter (ADC) on page 287 and I/O Ports on page 307.
Port C I/O pins (PTC5PTC0)
PTC5-PTC3 and PTC1-PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special function port that shares its pin with the system clock. See I/O Ports on page 307.
Port D I/O pins (PTD7PTD0)
Port D is an 8-bit special function port that shares two of its pins with the timer interface modules (TIMA and TIMB). see Timer Interface Module A (TIMA) on page 231 and Timer Interface Module B (TIMB) on page 257. PTD6-PTD0 also share pins with the analog to digital convertor (ADC) like port A if the 15-channel ADC is selected.
Port E I/O pins (PTE7/SPSCKPTE0/ TxD)
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), four of its pins with the Serial Peripheral Interface Module (SPI), and two of its pins with the Serial Communication Interface Module (SCI). See Serial Communications Interface Module (SCI) on page 163, Serial Peripheral Interface Module (SPI) on page 197, Timer Interface Module A (TIMA) on page 231 and I/O Ports on page 307.
Port F I/O pins (PTF6PTF0/TACH2)
Port F is a 7-bit special function port that shares four of its pins with the timer interface modules. SeeTimer Interface Module A (TIMA) on page 231, Timer Interface Module B (TIMB) on page 257 and I/O Ports on page 307.
MC68HC08AZ32 16 General Description
8-gen
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General Description Pin Assignments
Port G I/O pins (PTG2/KBD2PTG0 /KBD0)
PTG2/KBD2-PTG0/KBD0 are general-purpose bidirectional I/O pins with Key Wakeup feature. See Keyboard Module (KB) on page 299 and I/O Ports on page 307.
Port H I/O pins (PTH1/KBD4PTH0/ KBD3)
PTH1/KBD4-PTH0/KBD3 are general-purpose bidirectional I/O pins with Key Wakeup feature. See Keyboard Module (KB) on page 299 and I/O Ports on page 307.
CAN transmit pin (CANTx)
CANTx is the digital output from the msCAN module. See msCAN08 Controller (msCAN08) on page 331.
CAN receive pin (CANRx)
CANRx is the digital input to the msCAN module. See msCAN08 Controller (msCAN08) on page 373
9-gen
MC68HC08AZ32 General Description 17
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General Description
Table 1. External pins summary
PIN NAME PTA7 PTA0 PTB7/ATD7 PTB0/ATD0 PTC5 - PTC0 PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBLCK-P TD0/ATD8 PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1 PTF4/TBCH0 FUNCTION General purpose I/O General purpose I/0 / ADC channel General purpose I/O General purpose I/O General purpose I/O / Timer External Input clock General purpose I/O/ Timer External Input clock General purpose Input General purpose I/0 / SPI clock General purpose I/0 / SPI data path General purpose I/0 / SPI data path General purpose I/0 / SPI Slave Select General purpose I/0 / Timer A channel 1 General purpose I/0 / TimerA channel 0 General purpose I/0 / SCI Receive Data General purpose I/0 / SCI Transmit Data General purpose I/O General purpose I/O /Timer B channel 1 General purpose I/0 / TimerB channel 0 DRIVER TYPE Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State (open drain) Dual State (open drain) Dual State (open drain) Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes HYSTERESIS RESET STATE Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z)
MC68HC08AZ32 18 General Description
10-gen
MOTOROLA
General Description Pin Assignments
Table 1. External pins summary (Continued)
PIN NAME PTF3 PTF2 PTF1/TACH3 PTF0/TACH2 PTG2/KBD2 PTG0/KBD0 PTH1/KBD4PTH0/KBD3 VDD VSS VDDA VSSA VREFH AVSS/VREFL VDDAREF OSC1 OSC2 CGMXFC IRQ RST CANRx CANTx FUNCTION General purpose I/0 General purpose I/0 General purpose I/0 /TimerA channel 3 General purpose I/0 /TimerA channel 2 General purpose I/0 with key wakeup feature General purpose I/0 with key wakeup feature Logical chip power supply Logical chip ground Analog power supply(CGM) Analog ground (CGM) ADC reference voltage ADC gnd & reference voltage ADC power supply External clock in External clock out PLL loop filter cap External interrupt request Reset msCAN serial Input msCAN serial output DRIVER TYPE Dual State Dual State Dual State Dual State Dual State Dual State NA NA NA NA NA NA NA NA NA NA NA NA NA Output HYSTERESIS Yes Yes Yes Yes Yes Yes NA NA NA NA NA NA NA NA NA NA NA NA YES NA RESET STATE Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) NA NA NA NA NA NA NA Input (Hi-Z) Output NA Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Output
Details of the clock connections to each of the modules on the MC68HC08AZ32 are shown in Table 3. A short description of each clock source is also given in Table 2.
11-gen
MC68HC08AZ32 General Description 19
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General Description
Table 2. Signal name conventions
Signal name CGMXCLK CGMOUT Bus clock SPSCK TACLK TBCLK Description Buffered version of OSC1 from clock generator module (CGM) PLL-based or OSC1-based clock output from CGM module) CGMOUT divided by two SPI serial clock (see SPSCK (serial clock) on page 221) External clock Input for TIMA (see TIMA clock pin (PTD6/TACLK) on page 245) External clock Input for TIMB (see TIMB clock Pin (PTD4/TBLCK) on page 269)
Table 3. Clock source summary
Module ADC msCAN COP CPU EEPROM ROM RAM SPI SCI TIMA TIMB PIT KBI CGMXCLK or bus clock CGMXCLK or CGMOUT CGMXCLK Bus clock CGMXCLK or bus clock Bus clock Bus clock SPSCK CGMXCLK Bus clock or PTD6/ATD14/TACLK Bus clock or PTD4/ATD12/TBLCK Bus clock Bus clock Clock source
MC68HC08AZ32 20 General Description
12-gen
MOTOROLA
General Description Ordering Information
Ordering Information
This section contains instructions for ordering the MC68HC08AZ32.
MC Order Numbers Table 4. MC Order Numbers
MC Order Number
MC68HC08AZ32CFU MC68HC08AZ32VFU MC68HC08AZ32MFU
Operating Temperature Range
- 40 C to + 85C - 40 C to + 105 C - 40 C to + 125 C
13-gen
MC68HC08AZ32 General Description 21
MOTOROLA
General Description
MC68HC08AZ32 22 General Description
14-gen
MOTOROLA
Memory Map
Memory Map
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I/O section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Introduction
The CPU08 can address 64K bytes of memory space. The memory map includes: * * * * * 1024 bytes of RAM 32,272 bytes of User ROM 512 bytes of EEPROM 48 bytes of user-defined vectors 224 bytes of monitor ROM
The following definitions apply to the memory map representation of reserved and unimplemented locations. * * Reserved -- Accessing a reserved location can have unpredictable effects on MCU operation. Unimplemented -- Accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled.
1-mem
MC68HC08AZ32 Memory Map 23
MOTOROLA
Memory Map
I/O section
Addresses $0000-$004F, shown in Figure 2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: * * * * * * * * * * * * $0500 to $057F - CAN control and message buffers. See msCAN08 Controller (msCAN08) on page 331. $FE00 - (SIM break status register, SBSR) $FE01 - (SIM reset status register, SRSR) $FE03 - (SIM break flag control register, SBFCR) $FE07 - (EPROM control register, EPMCR) $FE0C and $FE0D - (break address registers, BRKH and BRKL) $FE0E - (break status and control register, BRKSCR) $FE0F - (LVI status register, LVISR) $FE1C - (EEPROM non-volatile register, EENVR) $FE1D - (EEPROM control register, EECR) $FE1F - (EEPROM array configuration register, EEACR) $FFFF - (COP control register, COPCTL)
MC68HC08AZ32 24 Memory Map
2-mem
MOTOROLA
Memory Map I/O section
$0000 $004F $0050 $044F $0450 $04FF $0500 $057F $0580 $07FF $0800 $09FF $0A00 $0FFF $1000 $7FFF $8000 $BFFF $C000 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR) RESERVED RESERVED ROM (15,872 BYTES) ROM (16,384BYTES) UNIMPLEMENTED (28,672 BYTES) UNIMPLEMENTED (1536 BYTES) EEPROM (512 BYTES) UNIMPLEMENTED (640 BYTES) CAN CONTROL AND MESSAGE BUFFERS(128 BYTES) UNIMPLEMENTED (176 BYTES) RAM (1024 BYTES) I/O REGISTERS (80 BYTES)
Figure 1. MC68HC08AZ32 Memory map
3-mem
MC68HC08AZ32 Memory Map 25
MOTOROLA
Memory Map
$FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 $FEFF $FF00 $FFBF $FFC0 $FFCF $FFD0 $FFFF
UNIMPLEMENTED RESERVED RESERVED RESERVED RESERVED UNIMPLEMENTED BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED (12 BYTES) EEPROM NON-VOLATILE REGISTER (EENVR) EEPROM CONTROL REGISTER (EECR) RESERVED EEPROM ARRAY CONFIGURATION (EEACR) MONITOR ROM (224 BYTES)
UNIMPLEMENTED (192 BYTES)
ROM (16 BYTES)
VECTORS (48 BYTES)
Figure 1. MC68HC08AZ32 Memory map (Continued)
MC68HC08AZ32 26 Memory Map
4-mem
MOTOROLA
Memory Map I/O section
Addr.
Name R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W:
Bit 7 PTA7 PTB7 0 PTD7 DDRA7 DDRB7 MCLKE N DDRD7 PTE7 0 0 0 DDRE7 0 0 0 SPRIE SPRF Bit 7 LOOPS SCTIE R8 SCTE
6 PTA6 PTB6 0 PTD6 DDRA6 DDRB6 0 DDRD6 PTE6 PTF6 0 0 DDRE6 DDRF6 0 0 R 0 6 ENSCI TCIE T8 TC
5 PTA5 PTB25 PTC5 PTD5 DDRA5 DDRB5 DDRC5 DDRD5 PTE5 PTF5 0 0 DDRE5 DDRF5 0 0 SPMSTR OVRF 5 TXINV SCRIE R SCRF
4 PTA4 PTB4 PTC4 PTD4 DDRA4 DDRB4 DDRC4 DDRD4 PTE4 PTF4 0 0 DDRE4 DDRF4 0 0 CPOL MODF 4 M ILIE R IDLE
3 PTA3 PTB3 PTC3 PTD3 DDRA3 DDRB3 DDRC3 DDRD3 PTE3 PTF3 0 0 DDRE3 DDRF3 0 0 CPHA SPTE 3 WAKE TE ORIE OR
2 PTA2 PTB2 PTC2 PTD2 DDRA2 DDRB2 DDRC2 DDRD2 PTE2 PTF2 PTG2 0 DDRE2 DDRF2 DDRG2 0 SPWOM 0 2 ILTY RE NEIE NF
1 PTA1 PTB1 PTC1 PTD1 DDRA1 DDRB1 DDRC1 DDRD1 PTE1 PTF1 PTG1 PTH1 DDRE1 DDRF1 DDRG1 DDRH1 SPE SPR1 1 PEN RWU FEIE FE
Bit 0 PTA0 PTB0 PTC0 PTD0 DDRA0 DDRB0 DDRC0 DDRD0 PTE0 PTF0 PTG0 PTH0 DDRE0 DDRF0 DDRG0 DDRH0 SPTIE SPR0 Bit 0 PTY SBK PEIE PE
$0000 Port A Data Register (PTA) $0001 Port B Data Register (PTB) $0002 Port C Data Register
$0003 Port D Data Register (PTD) $0004 $0005 $0006 $0007 Data Direction Register A (DDRA) Data Direction RegisterB (DDRB) Data Direction Register C (DDRC) Data Direction Register D (DDRD)
$0008 Port E Data Register (PTE) $0009 Port F Data Register (PTF) $000A Port G Data Register (PTG) $000B Port H Data Register (PTH) $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 Data Direction Register E (DDRE) Data Direction Register F (DDRF) Data Direction Register G (DDRG) Data Direction Register (DDRH) SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR) SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1)
= Unimplemented
R
= Reserved
Figure 2. Control, status, and data registers (Sheet 1 of 5)
5-mem
MC68HC08AZ32 Memory Map 27
MOTOROLA
Memory Map
Addr. $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C
Name Bit 7 6 5 4 3 0 0 0 0 0 SCI Status Register 2 R: (SCS2) W: R: SCI Data Register (SCDR) Bit 7 6 5 4 3 W: 0 0 0 SCI Baud Rate Register R: SCP1 SCP0 (SCBR) W: IRQF IRQ Status and Control R: Register (ISCR) W: 0 0 0 0 KEYF Keyboard Status/Control R: (KBSCR) W: PLLF 1 PLL Control Register R: PLLIE PLLON BCS (PCTL) W: LOCK 0 PLL Bandwidth Control R: AUTO ACQ XLD Register (PBWC) W: PLL Programming Register R: MUL7 MUL6 MUL5 MUL4 VRS7 (PPG) W: Mask Option Register A R: LVISTOP ROMSEC LVIRSTD LVIPWRD SSREC (MORA) W: R R R R R TOF 0 0 Timer A Status and Control R: TOIE TSTOP Register (TASC) W: 0 TRST Keyboard Interrupt Enable R; KBIE4 KBIE3 Register (KBIER) W: 14 13 12 11 Timer A Counter Register R: Bit 15 High (TACNTH) W; Bit 7 6 5 4 3 Timer A Counter Register R: Low (TACNTL) W: TimerA Modulo Register R: Bit 15 14 13 12 11 High (TAMODH) W: TimerA Modulo Register R: Bit 7 6 5 4 3 Low (TAMODL) W: Timer A Channel 0 Status R: CH0F and Control Register CH0IE MS0B MS0A ELS0B W: 0 (TASC0) TimerA Channel 0 Register R: Bit 15 14 13 12 11 High (TACH0H) W: Timer A Channel 0 R: Bit 7 6 5 4 3 Register Low (TACH0L) W: Timer A Channel 1 Status R: CH1F 0 and Control Register CH1IE MS1A ELS1B W: 0 (TASC1) Timer A Channel 1 R: Bit 15 14 13 12 11 Register High (TACH1H) W: Timer A Channel 1 R: Bit 7 6 5 4 3 Register Low (TACH1L) W: Timer A Channel 2 Status R: CH2F and Control Register CH2IE MS2B MS2A ELS2B W: 0 (TASC2) = Unimplemented R
2 0 2 SCR2 0 ACK1 0 ACKK 1 0 VRS6 COPRS R PS2 KBIE2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 ELS2A
1 BKF 1 SCR1 IMASK1
Bit 0 RPF Bit 0 SCR0 MODE1
IMASKK MODEK 1 0 VRS5 STOP R PS1 KBIE1 9 1 9 1 TOV0 9 1 TOV1 9 1 TOV2 1 0 VRS4 COPD R PS0 KBIE0 Bit 8 Bit 0 Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX
= Reserved
Figure 2. Control, status, and data registers (Sheet 2 of 5)
MC68HC08AZ32 28 Memory Map
6-mem
MOTOROLA
Memory Map I/O section
Addr. $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B
Name Timer A Channel 2 Register High (TACH2H) Timer A Channel 2 Register Low (TACH2L) Timer Channel 3 Status and Control Register (TASC3) Timer Channel 3 Register High (TACH3H) Timer Channel 3 Register Low (TACH3L)
Bit 7 R: W: R: W: R: W: Bit 15 Bit 7 CH3F 0 Bit 15 Bit 7
6 14 6 CH3IE 14 6
5 13 5 MS3B 13 5
4 12 4 MS3A 12 4
3 11 3 ELS3B 11 3
2 10 2 ELS3A 10 2
1 9 1 TOV3 9 1
Bit 0 Bit 8 Bit 0 CH3MAX Bit 8 Bit 0
R: W: R: W: R: Unimplemented W: R: Unimplemented W: R: Unimplemented W: R: Unimplemented W: R: Unimplemented W: R: Unimplemented W: R: ADSCR W: R: ADR W: R: ADC Input Clock Select (ADCLKR) W: R: Reserved W: R: W: R: W: R: W: R: W: R: W: R: W:
COCO
R
AD7 ADIV2 R
AIEN AD6 ADIV1 R
ADCO AD5 ADIV0 R
CH4 AD4 ADICLK R
CH3 AD3 0
CH2 AD2 0
CH1 AD1 0
CH0 AD0 0
R
R
R
R
$003C $003D $003E $003F $0040 $0041
Reserved Unimplemented Unimplemented Mask Option Register B (MORB) TimerB Status and Control Register (TBSC) TimerB Counter Register High (TBCNTH)
R
R
R
R
R
R
R
R
R TOF 0 Bit 15
R TOIE 14
EESEC TSTOP 13
R 0 TRST 12
R 0 11
R PS2 10
R PS1 9
R PS0 8
= Unimplemented
R
= Reserved
Figure 2. Control, status, and data registers (Sheet 3 of 5)
7-mem
MC68HC08AZ32 Memory Map 29
MOTOROLA
Memory Map
Addr. $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F
Name TimerB Counter Register Low (TBCNTL) TimerB Modulo Register High (TBMODH) TimerB Modulo Register Low (TBMODL) Timer B Channel 0Status and Control Register (TBSC0) Timer B Channel 0Register High (TBCH0H) Timer B Channel 0Register Low (TBCH0L) Timer B Channel 1Status/ Control Register (TBSC1) Timer B Channel 1Register High (TBCH1H) Timer B Channel1Register Low (TBCH1L) Programmable Interrupt Timer Status & Control Register (PSC) PIT Counter Register HIGH) (PCNTH) PIT Counter Register Low (PCNTL) PIT Modulo Register High (PMODH) PIT Modulo Register Low (PMODL) SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR)
R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W: R: W R W R: W R: W: R: W:
Bit 7 Bit 7 Bit 15 Bit 7 CH4F 0 Bit 15 Bit 7 CH5F 0 Bit 15 Bit 7 POF 0 Bit 15 7 Bit 15 7
6 6 14 6 CH4IE 14 6 CH5IE 14 6 PIE 14 6 14 6
5 5 13 5 MS4B 13 5 MS5B 13 5 PSTOP 13 5 13 5
4 4 12 4 MS4A 12 4 MS5A 12 4 0 PRST 12 4 12 4
3 3 11 3 ELS4B 11 3 ELS5B 11 3 0
2 2 10 2 ELS4A 10 2 ELS5A 10 2 PPS2
1 1 9 1 TOV4 9 1 TOV5 9 1 PPS1 9 1 9 1
Bit 0 0 Bit 8 Bit 0 CH0MAX 8 0 CH1MAX 8 0 PPS0 8 0 8 0
11 3 11 3
10 2 10 2
$FE00 $FE01
R POR
R PIN
R COP
R ILOP
R ILAD
R 0
SBSW LVI
R 0
$FE03
SIM Break Flag Control R: Register (SBFCR) W: Reserved Break Address Register High (BRKH) Break Address Register Low (BRKL) R: W: R: W: R: W:
BCFE
R
R
R
R
R
R
R
$FE07 $FE0C $FE0D
Bit 15 Bit 7
14 6
13 5
12 4
11 3 R
10 2 = Reserved
9 1
Bit 8 Bit 0
= Unimplemented
Figure 2. Control, status, and data registers (Sheet 4 of 5)
MC68HC08AZ32 30 Memory Map
8-mem
MOTOROLA
Memory Map I/O section
Name Bit 7 Break Status and Control R: $FE0E BRKE Register (BRKSCR) W: R: LVIOUT $FE0F LVI Status Register (LVISR) W: $FE1C $FE1D $FE1E $FE1F EENVR EECR Reserved EEACR R: EERA W: R: EEBCLK W: R: R W: R: EERA W:
Addr.
6 BRKA 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
CON2 0 R CON2
CON1 EEOFF R CON1
CON0
EEPB3
EEPB2 ELAT R EEBP2
EEPB1 0 R EEBP1
EEPB0 EEPGM R EEBP0
EERAS1 EERAS0 R CON0 R EEBP3
$FFFF
COP Control Register R: (COPCTL) W:
LOW BYTE OF RESET VECTOR WRITING TO $FFFF CLEARS COP COUNTER = Unimplemented R = Reserved
Figure 2. Control, status, and data registers (Sheet 5 of 5)
9-mem
MC68HC08AZ32 Memory Map 31
MOTOROLA
Memory Map
Table 1. Vector addresses (1)
Address Vector ADC vector (high) ADC vector (low) Keyboard vector (high) Keyboard vector (low) SCI transmit vector (high) SCI Transmit vector (Low) SCI Receive vector (High) SCI Receive vector (Low) SCI Error vector (High) SCI Error vector (Low) msCAN Transmit vector(High) msCAN Transmit vector (Low) msCAN Receive vector(High) msCAN Receive vector (Low) msCAN Error vector(High) msCAN Error vector (Low) msCAN Wakeup vector(High) msCAN Wakeup vector (Low) SPI Transmit vector(High) SPI Transmit vector (Low) SPI Receive vector(High) SPI Receive vector (Low) TIMB Overflow vector(High) TIMB Overflow vector (Low) TIMB CH1 vector(High) TIMB CH1 vector (Low) TIMB CH0 vector(High) TIMB CH0 vector (Low) TIMA Overflow vector(High) TIMA Overflow vector (Low) TIMA CH3 vector(High) TIMA CH3 vector (Low) TIMACH2 vector(High) TIMA CH2 vector (Low) TIMA CH1 vector(High) TIMA CH1 vector (Low) TIMA CH0 vector(High) TIMA CH0 vector (Low) PIT vector(High) PIT vector (Low) PLL vector(High) PLL vector (Low) IRQ vector (High) IRQ vector (Low) SWI vector(High) SWI vector (Low) Reset vector (High) Reset vector (Low) 10-mem
Low
$FFD0 $FFD1 $FFD2 $FFD3 $FFD4 $FFD5 $FFD6 $FFD7 $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF
High
MC68HC08AZ32 32 Memory Map
Priority
MOTOROLA
Memory Map I/O section
1. All available ROM locations not defined by the user will by default be filled with the software interrupt (SWI, opcode 83) instruction - see Central Processor Unit (CPU). Take this into account when defining vector addresses. It is recommended that ALL vector addresses are defined.
11-mem
MC68HC08AZ32 Memory Map 33
MOTOROLA
Memory Map
MC68HC08AZ32 34 Memory Map
12-mem
MOTOROLA
RAM RAM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Introduction
This section describes the 1024 bytes of RAM.
Functional description
Addresses $0050 through $044F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64K byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations.
Within page zero there are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides an ideal location for frequently accessed global variables. Before processing an interrupt, the CPU uses 5 bytes of the stack to save the contents of the CPU registers.
NOTE:
1-ram
For M6805 compatibility, the H register is not stacked.
MC68HC08AZ32 RAM 35
MOTOROLA
RAM
During a subroutine call, the CPU uses 2 bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Care should be taken when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
MC68HC08AZ32 36 RAM
2-ram
MOTOROLA
ROM ROM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Introduction
This section describes the operation of the embedded ROM memory.
Functional description
The user ROM consists of up to 32, 272 bytes from addresses $8000-$FDFF and $FFC0-$FFCF. The monitor ROM and vectors are located from $FE20-$FEFF. Forty-eight user vectors, $FFD0-$FFFF, are dedicated to user-defined reset and interrupt vectors.
Security
Security has been incorporated into the MC68HC08AZ32 to prevent external viewing of the ROM contents1. This feature is selected by a mask option and ensures that customer-developed software remains propriety. See Mask Options on page 119.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users.
1-rom
MC68HC08AZ32 ROM 37
MOTOROLA
ROM
MC68HC08AZ32 38 ROM
2-rom
MOTOROLA
EEPROM
EEPROM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EEPROM programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EEPROM erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 EEPROM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MCU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MC68HC08AZ32 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . 45 EEPROM control register (EECR) . . . . . . . . . . . . . . . . . . . . . . . . . 46 EEPROM non-volatile register (EENVR) and EEPROM array configuration register (EEACR) . . . . . . . . . . . . . . . . . . . . . . . 48 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1-eeprom
MC68HC08AZ32 EEPROM 39
MOTOROLA
EEPROM
Introduction
This section describes the electrically erasable programmable ROM (EEPROM).
Future EEPROM Memory
Design is underway to introduce an improved EEPROM module, which will simplify programming and erase. Current read, write and erase algorithms are fully compatible with the new EEPROM design. The new EEPROM module requires a constant timebase through the set up of new timebase control registers. If more information is required for code compatibility please contact the factory. The silicon differences will be identified by mask set. Please read Appendix C: Future EEPROM Registers for preliminary details.
NOTE:
This new silicon will not allow multiple writes before erase. EEPROM bytes must be erased before reprogramming.
Features
* * * * Byte, block or bulk erasable Non-volatile block protection option Non-volatile MCU configuration bits On-chip charge pump for programming/erasing.
MC68HC08AZ32 40 EEPROM
2-eeprom
MOTOROLA
EEPROM Functional description
Functional description
512 bytes of EEPROM can be programmed or erased without an external voltage supply. The EEPROM has a lifetime of 10,000 write-erase cycles. EEPROM cells are protected with a non-volatile block protection option. These options are stored in the EEPROM non-volatile register (EENVR) and are loaded into the EEPROM array configuration register after reset (EEACR) or after a read of EENVR. Hardware interlocks are provided to protect stored data corruption from accidental programming/erasing. The EEPROM array will leave the factory in the erased state all addresses logic `1', and bit 4 of the EENVR register will be programmed to #1 such that the full array is available and unprotected.
EEPROM programming
The unprogrammed state is a logic `1'. Programming changes the state to a logic `0'. Only valid EEPROM bytes in the non-protected blocks and EENVR can be programmed. It is recommended that all bits should be erased before being programmed. The following procedure describes how to program a byte of EEPROM: 1. Clear EERAS1 and EERAS0 and set EELAT in the EECR (See Note a. and b.) 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See Note c.) 4. Wait for a time, tEEPGM, to program the byte. 5. Clear EEPGM bit. 6. Wait for the programming voltage time to fall (tEEFPV). 7. Clear EELAT bits. (See Note d.) 8. Repeat steps 1 to 7 for more EEPROM programming.
3-eeprom
MC68HC08AZ32 EEPROM 41
MOTOROLA
EEPROM
NOTES: a. EERAS1 and EERAS0 must be cleared for programming, otherwise the part will be in erase mode b. Setting the EELAT bit configures the address and data buses to latch data for programming the array. Only data with a valid EEPROM address will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. Any attempts to read other EEPROM data will result in the latched data being read. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write. c. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper programming sequence. When EEPGM is set, the on-board charge pump generates the program voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the program voltage is removed from the array and the internal charge pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. e. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
EEPROM erasing
The unprogrammed state is a logic `1'. Only the valid EEPROM bytes in the non-protected blocks and EENVR can be erased. The following procedure shows how to erase EEPROM: 1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase, and set EELAT in EECR (see Note f.) 2. Write any data to the desired address for byte erase, to any address in the desired block for block erase, or to any array address for bulk erase. 3. Set the EEPGM bit. (See Note g.) 4. Wait for a time, tbyte/tblock/tbulk before erasing the
MC68HC08AZ32 42 EEPROM
4-eeprom
MOTOROLA
EEPROM Functional description
byte/block/array. 5. Clear EEPGM bit. 6. Wait for the erasing voltage time to fall (tEEFPV). 7. Clear EELAT bits. (See Note h.) 8. Repeat steps 1 to 7 for more EEPROM byte/block erasing. The EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the corresponding block cannot be erased and bulk erase mode does not apply. NOTES: f. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses with its data will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. In block erase mode, any EEPROM address in the block may be used in step 2. All locations within this block will be erased. In bulk erase mode, any EEPROM address may be used to erase the whole EEPROM. EENVR is not affected with block or bulk erase. Any attempts to read other EEPROM data will result in the latched data being read. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write.
g. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified. If EEPGM is set, the on-board charge pump generates the erase voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. h. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array. In general, all bits should be erased before being programmed.
5-eeprom
MC68HC08AZ32 EEPROM 43
MOTOROLA
EEPROM
EEPROM block protection The 512 bytes of EEPROM is divided into four 128 byte blocks. Each of these blocks can be separately protected by the EEBPx bit. Any attempt to program or erase memory locations within the protected block will not allow the program/erase voltage to be applied to the array. Table 2 shows the address ranges within the blocks. Table 2. EEPROM array address blocks
BLOCK NUMBER (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 ADDRESS RANGE $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF
If the EEBPx bit is set, the corresponding address block is protected. These bits are effective after a reset or a read to EENVR register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EENVR register and then reading the EENVR register.
EEPROM configuration
The EEPROM non-volatile register (EENVR) contains configurations concerning block protection and redundancy. EENVR is physically located on the bottom of the EEPROM array. The contents are non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration into a corresponding volatile EEPROM array configuration register (EEACR). Thereafter, all reads to the EENVR will result in EEACR being reloaded. The EEPROM configuration can be changed by programming/erasing the EENVR like a normal EEPROM byte. The new array configuration will take effect with a system reset or a read of the EENVR.
MCU configuration
The EEPROM non-volatile register (EENVR) also contains general purpose bits which can be used to enable/disable functions within the MCU which, for safety reasons, need to be controlled from non-volatile
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EEPROM Functional description
memory. On reset, this special register loads the MCU configuration into the volatile EEPROM array configuration register (EEACR). Thereafter, all reads to the EENVR will result in EEACR being reloaded. The MCU configuration can be changed by programming/erasing the EENVR like a normal EEPROM byte. Please note that it is the users responsibility to program the EENVR register to the correct system requirements and verify it prior to use. The new array configuration will take effect with a system reset or a read of the EENVR.
MC68HC08AZ32 EEPROM Security
The MC68HC08AZ32 has a special security option which prevents program/erase access to memory locations $08F0 to $08FF. This security function is enabled by programming the CON0 bit in the EENVR to 0. In addition to disabling the program and erase operations on memory locations $08F0 to $08FF the enabling of the security option has the following effects: * * * * * Bulk and block erase modes are disabled. Programming and erasing of the EENVR is disabled. Non secure locations ($0800-$08EF) can be erased using the single byte erase function as normal. Secured locations can be read as normal. Writing to a secured location no longer qualifies as a "valid EEPROM write" as detailed in EEPROM programming Note a., and EEPROM erasing Note f.
NOTE:
Once armed, the security is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled.
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EEPROM
EEPROM control register (EECR) This read/write register controls programming/erasing of the array.
7 EECR $FE1D READ: EEBCLK WRITE: RESET: 0
6 0
5 EEOFF
4
3
2 EELAT 0
1 0
0 EEPGM
EERAS1 EERAS0 0 0
0
0
0
0
= Unimplemented
Figure 1. EEPROM control register (EECR) EEBCLK -- EEPROM BUS CLOCK ENABLE This read/write bit determines which clock will be used to drive the internal charge pump for programming/erasing. Reset clears this bit. 1 = Bus clock drives charge pump 0 = Internal RC oscillator drives charge pump
NOTE:
It is recommended that the internal RC oscillator is used to drive the internal charge pump for applications which have a bus frequency of less than 8MHz.
EEOFF -- EEPROM power down This read/write bit disables the EEPROM module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM array 0 = Enable EEPROM array
NOTE:
The EEPROM requires a recovery time tEEOFF to stabilize after clearing the EEOFF bit.
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EEPROM Functional description
EERAS1-EERAS0 -- Erase bits These read/write bits set the erase modes. Reset clears these bits. Table 3. EEPROM program/erase mode select
EEBPx 0 0 0 0 1 EERAS1 0 0 1 1 X EERA0 0 1 0 1 X X = don't care MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program
EELAT -- EEPROM latch control This read/write bit latches the address and data buses for programming the EEPROM array. EELAT can not be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation EEPGM -- EEPROM program/erase enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off
NOTE:
Writing `0's to both the EELAT and EEPGM bits with a single instruction will only clear EEPGM. This is to allow time for the removal of high voltage.
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EEPROM
EEPROM non-volatile register (EENVR) and EEPROM array configuration register (EEACR)
7 EENVR $FE1C READ: EERA WRITE: RESET: PV PV PV PV PV PV PV PV CON2 CON1 CON0 EEBP3 EEBP2 EEBP1 EEBP0 6 5 4 3 2 1 0
PV = Programmed Value or `1' in the erased state.
Figure 2. EEPROM non-volatile register (EENVR)
7 EEACR $FE1F READ: WRITE: RESET: EENVR EENVR EENVR EENVR EENVR EENVR EENVR EENVR EERA 6 CON2 5 CON1 4 CON0 3 EEBP3 2 EEBP2 1 EEBP1 0 EEBP0
= Unimplemented
Figure 3. EEPROM array control register (EEACR) EERA -- EEPROM redundant array This bit is reserved for future use and should always be equal to 0. CONx -- MCU configuration bits These read/write bits can be used to enable/disable functions within the MCU. Reset loads CONx from EENVR to EEACR. CON2 -- Unused CON1 -- Unused CON0 -- EEPROM security 1 = EEPROM security disabled 0 = EEPROM security enabled EEBP3-EEBP0 -- EEPROM block protection bits. These read/write bits prevent blocks of EEPROM array from being programmed or erased. Reset loads EEBP[3:0] from EENVR to EEACR. 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected
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EEPROM Functional description
Low power modes
The WAIT and STOP instructions can put the MCU in low power consumption standby modes. The WAIT instruction does not affect the EEPROM. It is possible to program the EEPROM and put the MCU in WAIT mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit before executing the WAIT instruction. The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction should not be executed while the high voltage is turned on (EEPGM=1). If STOP mode is entered while program/erase is in progress, high voltage will automatically be turned off. However, the EEPGM bit will remain set. When STOP mode is terminated, if EEPGM is still set, the high voltage will automatically be turned back on. Program/erase time will need to be extended if program/erase is interrupted by entering STOP mode. The module requires a recovery time tEESTOP to stabilize after leaving STOP mode. Attempts to access the array during the recovery time will result in unpredictable behavior.
WAIT mode
STOP mode
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EEPROM
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Central Processor Unit (CPU) Central Processor Unit (CPU)
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Arithmetic/logic unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Introduction
This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
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Central Processor Unit (CPU)
Features
Features of the CPU include the following: * * * * * * * * * * Full upward, object-code compatibility with M68HC05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 8.4MHz CPU internal bus frequency 64K byte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Low-power STOP and WAIT Modes
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Central Processor Unit (CPU) CPU registers
CPU registers
Figure 1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 1. CPU registers Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: A Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 1. Accumulator (A)
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Central Processor Unit (CPU)
Index register (H:X) The 16-bit index register allows indexed addressing of a 64K byte memory space. H is the upper byte of the index register and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
Bit 15 Read: H:X Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
X = Indeterminate
Figure 1. Index register (H:X) The index register can also be used as a temporary data storage location.
Stack pointer (SP)
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SP Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Figure 1. Stack pointer (SP)
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Central Processor Unit (CPU) CPU registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations.
Program counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PC Write: Reset: Loaded with vector from $FFFE and $FFFF
Figure 1. Program counter (PC)
Condition code register (CCR)
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to `1'. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: 6 5 4 3 2 1 Bit 0
CCR Write: Reset:
V
X
1
1
1
1
H
X
I
1
N
X
Z
X
C
X
X = Indeterminate
Figure 1. Condition code register (CCR)
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Central Processor Unit (CPU)
V -- Overflow flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-carry flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
NOTE:
To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first. A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI).
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Central Processor Unit (CPU) Arithmetic/logic unit (ALU)
N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/borrow flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
Arithmetic/logic unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture.
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Central Processor Unit (CPU)
CPU during break interrupts
If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See Break Module on page 123. The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
Instruction Set Summary
Table 1 provides a summary of the M68HC08 instruction set.
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Central Processor Unit (CPU) Instruction Set Summary
Table 1 Instruction Set Summary
Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operand
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff rr
Address Mode
Opcode
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT - IX2 IX1 IX SP1 SP2 IMM DIR EXT - IX2 IX1 IX SP1 SP2 - - - - - - IMM - - - - - - IMM IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 DIR INH - - INH IX1 IX SP1 DIR INH - - INH IX1 IX SP1 - - - - - - REL
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
Logical AND
A (A) & (M)
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24
Arithmetic Shift Right
b7 b0
C
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
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Cycles
Effect on CCR
Central Processor Unit (CPU)
Table 1 Instruction Set Summary (Continued)
Source Form Operand
dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr
Address Mode
Opcode
Operation
Description
VH I NZC
BCLR n, opr
Clear Bit n in M
Mn 0
DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL
11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D
4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
Bit Test
(A) & (M)
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
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Cycles
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 1 Instruction Set Summary (Continued)
Source Form
BNE rel BPL rel BRA rel
Operand
rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
Address Mode
Opcode
Operation
Description
PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel
VH I NZC
Branch if Not Equal Branch if Plus Branch Always
- - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00
- - - - - - REL
AD
4
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask
DIR IMM - - - - - - IMM IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
31 41 51 61 71 9E61 98 9A
5 4 4 5 4 6 1 2 3 1 1 1 3 2 4
Clear
3F dd 4F 5F 8C 6F ff 7F 9E6F ff
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Cycles
Effect on CCR
Central Processor Unit (CPU)
Table 1 Instruction Set Summary (Continued)
Source Form
CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operand
ii dd hh ll ee ff ff ff ee ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff dd rr rr rr ff rr rr ff rr ii dd hh ll ee ff ff ff ee ff
Address Mode
Opcode
Operation
Description
VH I NZC
Compare A with M
(A) - (M)
IMM DIR EXT - - IX2 IX1 IX SP1 SP2 DIR INH 0 - - 1 INH IX1 IX SP1 - - IMM DIR IMM DIR EXT - - IX2 IX1 IX SP1 SP2 U - - INH
A1 B1 C1 D1 E1 F1 9EE1 9ED1
2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B
Compare H:X with M
Compare X with M
(X) - (M)
Decimal Adjust A
(A)10
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - - - IX1 IX SP1 - - - - INH IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
Decrement
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8
Divide
Exclusive OR M with A
A (A M)
MC68HC08AZ32 62 Central Processor Unit (CPU)
12-cpu
MOTOROLA
Cycles
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 1 Instruction Set Summary (Continued)
Source Form
INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL
Operand
dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Address Mode
Opcode
Operation
Description
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
VH I NZC
Increment
DIR INH - - - INH IX1 IX SP1 DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 0 - - - IMM DIR IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 DIR INH - - INH IX1 IX SP1 DIR INH - - 0 INH IX1 IX SP1 DD 0 - - - DIX+ IMD IX+D - 0 - - - 0 INH
3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE
4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5
Jump
PC Jump Address
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
Load H:X from M
H:X (M:M + 1)
Load X from M
X (M)
Logical Shift Left (Same as ASL)
C b7 b0
0
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42
Logical Shift Right
0 b7 b0
C
Move
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A)
Unsigned multiply
13-cpu
MC68HC08AZ32 Central Processor Unit (CPU) 63
MOTOROLA
Cycles
Effect on CCR
Central Processor Unit (CPU)
Table 1 Instruction Set Summary (Continued)
Source Form
NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operand
ii dd hh ll ee ff ff ff ee ff
Address Mode
Opcode
Operation
Description
VH I NZC
M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
Negate (Two's Complement)
DIR INH - - INH IX1 IX SP1 - - - - - - INH - - - - - - INH IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2 - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH - - INH IX1 IX SP1 DIR INH - - INH IX1 IX SP1 - - - - - - INH
30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2 2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1
No Operation Nibble Swap A
Inclusive OR A and M
A (A) | (M)
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
Rotate Left through Carry
C b7 b0
Rotate Right through Carry
b7 b0
C
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
RTI
Return from Interrupt
INH
80
7
RTS
Return from Subroutine
- - - - - - INH
81
4
MC68HC08AZ32 64 Central Processor Unit (CPU)
14-cpu
MOTOROLA
Cycles
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 1 Instruction Set Summary (Continued)
Source Form
SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Operand
ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff
Address Mode
Opcode
Operation
Description
VH I NZC
Subtract with Carry
A (A) - (M) - (C)
IMM DIR EXT - - IX2 IX1 IX SP1 SP2 - - - - - 1 INH - - 1 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 0 - - - DIR - - 0 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 IMM DIR EXT - - IX2 IX1 IX SP1 SP2
A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0
2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Set Carry Bit Set Interrupt Mask
C1 I1
Store A in M
M (A)
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
Store X in M
M (X)
Subtract
A (A) - (M)
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
- - 1 - - - INH
83
9
TAP TAX TPA
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH
84 97 85
2 1 1
15-cpu
MC68HC08AZ32 Central Processor Unit (CPU) 65
MOTOROLA
Cycles
Effect on CCR
Central Processor Unit (CPU)
Table 1 Instruction Set Summary (Continued)
Source Form
TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS
Operand
Address Mode
Opcode
Operation
Description
VH I NZC
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
DIR INH 0 - - - INH IX1 IX SP1 - - - - - - INH - - - - - - INH - - - - - - INH
3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94
3 1 1 3 2 4 2 1 2
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1
A Accumulatorn C Carry/borrow bitopr CCRCondition code registerPC ddDirect address of operandPCH dd rrDirect address of operand and relative offset of branch instructionPCL DDDirect to direct addressing modeREL DIRDirect addressing moderel DIX+Direct to indexed with post increment addressing moderr ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 EXTExtended addressing modeSP2 ff Offset byte in indexed, 8-bit offset addressingSP H Half-carry bitU H Index register high byteV hh llHigh and low bytes of operand address in extended addressingX I Interrupt maskZ ii Immediate operand byte& IMDImmediate source to direct destination addressing mode| IMMImmediate addressing mode INHInherent addressing mode( ) IXIndexed, no offset addressing mode-( ) IX+Indexed, no offset, post increment addressing mode# IX+DIndexed with post increment to direct addressing mode IX1Indexed, 8-bit offset addressing mode IX1+Indexed, 8-bit offset, post increment addressing mode? IX2Indexed, 16-bit offset addressing mode: MMemory location N Negative bit--
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
Opcode Map
MC68HC08AZ32 66 Central Processor Unit (CPU)
16-cpu
MOTOROLA
Cycles
Effect on CCR
17-cpu
DIR 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F INH Read-Modify-Write INH IX1 SP1 IX IMM DIR EXT IX1 SP1 IX Control INH INH Register/Memory IX2 SP2 2 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
MSB LSB
Bit Manipulation DIR DIR
Branch REL
MSB
0
1
MOTOROLA
1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX 7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1 2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX 0 Low Byte of Opcode in Hexadecimal 0 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment High Byte of Opcode in Hexadecimal 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
LSB
0
1
2
3
4
5
6
7
8
9
A
Central Processor Unit (CPU)
B
C
D
E
F
5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
Central Processor Unit (CPU) Opcode Map
MC68HC08AZ32
Table 2: Opcode Map
67
Central Processor Unit (CPU)
MC68HC08AZ32 68 Central Processor Unit (CPU)
18-cpu
MOTOROLA
System Integration Module (SIM) SIM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIM bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . 72 Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Clock start-up from POR or LVI reset . . . . . . . . . . . . . . . . . . . . . . . 73 Clocks in STOP and WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 External pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Active resets from internal sources. . . . . . . . . . . . . . . . . . . . . . . . . 75 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Computer operating properly (COP) reset . . . . . . . . . . . . . . . . . 77 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Low-voltage inhibit (LVI) reset . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SIM counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SIM counter during power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . 79 SIM counter during STOP mode recovery . . . . . . . . . . . . . . . . . . . 79 SIM counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SWI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . 84 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SIM break status register (SBSR). . . . . . . . . . . . . . . . . . . . . . . . . . 88 SIM reset status register (SRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SIM break flag control register (SBFCR) . . . . . . . . . . . . . . . . . . . . 90
1-sim
MC68HC08AZ32 System Integration Module (SIM) 69
MOTOROLA
System Integration Module (SIM)
Introduction
This section describes the system integration module, which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 1. Table 1 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - STOP/WAIT/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
MC68HC08AZ32 70 System Integration Module (SIM)
2-sim
MOTOROLA
System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK
CGMXCLK (FROM CGM) CGMOUT (FROM CGM)
/2
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 1. SIM block diagram Table 1. SIM I/O register summary
Register Name SIM Break Status Register (SBSR) Bit 7 R 6 R PIN 0 5 R COP 0 4 R ILOP 0 3 R ILAD 0 2 R 0 0 1 SBSW LVI 0 Bit 0 Addr. R 0 0 $FE00 $FE01 $FE03
SIM Reset Status Register (SRSR) POR SIM Break Flag Control Register (SBFCR) BCFE R
= Reserved for factory test
Table 2 shows the internal signal names used in this section.
3-sim
MC68HC08AZ32 System Integration Module (SIM) 71
MOTOROLA
System Integration Module (SIM)
Table 2. Signal naming conventions
Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W Description Buffered version of OSC1 from clock generator module (CGM) PLL output PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
SIM bus clock control and generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 2. This clock can come from either an external oscillator or from the on-chip PLL. See Clock Generator Module (CGM) on page 91.
OSC1 CLOCK SELECT CIRCUIT
CGMXCLK
SIM COUNTER
CGMVCLK
/2
A B S*
CGMOUT
/2
BUS CLOCK GENERATORS
*When S = 1,
CGMOUT = B PLL BCS PTC3 MONITOR MODE USER MODE
SIM
CGM
Figure 2. CGM clock signals
MC68HC08AZ32 72 System Integration Module (SIM)
4-sim
MOTOROLA
System Integration Module (SIM) SIM bus clock control and generation
Bus timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. See Clock Generator Module (CGM) on page 91.
Clock start-up from POR or LVI reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has been completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
Clocks in STOP and WAIT mode
Upon exit from STOP mode (by an interrupt, break, or reset), the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the STOP delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP mode on page 86. In WAIT mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the WAIT mode subsection of each module to see if the module is active or inactive in WAIT mode. Some modules can be programmed to be active in WAIT mode.
5-sim
MC68HC08AZ32 System Integration Module (SIM) 73
MOTOROLA
System Integration Module (SIM)
Reset and system initialization
The MCU has the following reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address
All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter, see SIM counter on page 79, but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See SIM registers on page 88.
External pin reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 3 for details. Figure 3 shows the relative timing. Table 3. PIN bit set timing
Reset type POR/LVI All others Number of cycles required to set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
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System Integration Module (SIM) Reset and system initialization
CGMOUT
RST
IAB
PC
VECT H
VECT L
Figure 3. External reset timing
Active resets from internal sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow for resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 4. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 5. Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles, during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST as shown in Figure 4.
IRST RST PULLED LOW BY MCU 32 CYCLES CGMXCLK 32 CYCLES
RST
IAB
VECTOR HIGH
Figure 4. Internal reset timing
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System Integration Module (SIM)
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET
Figure 5. Sources of internal reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. Power-on reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * * * A POR pulse is generated The internal reset signal is asserted The SIM enables CGMOUT Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow the oscillator to stabilize The RST pin is driven low during the oscillator stabilization time The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared
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System Integration Module (SIM) Reset and system initialization
OSC1
PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 6. POR recovery Computer operating properly (COP) reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, a value (any value) should be written to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 4 of the SIM counter. The SIM counter output, which occurs at least every 213 - 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VDD + VHI on the RST pin disables the COP module.
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System Integration Module (SIM)
Illegal opcode reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the STOP enable bit, STOP, in the mask option register is logic `0', the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. Illegal address reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
NOTE:
Extra care should be exercised if code in this port has been taken from another HC08 with a different memory map since some legal addresses could become illegal addresses on a smaller ROM. It is the user's responsibility to check their code for illegal addresses.
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources.
Low-voltage inhibit (LVI) reset
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System Integration Module (SIM) SIM counter
SIM counter
The SIM counter is used by the power-on reset module (POR) and in STOP mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
SIM counter during power-on reset
The power-on reset (POR) module detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine.
SIM counter during STOP mode recovery
The SIM counter is also used for STOP mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short STOP recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic `1', then the STOP recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from STOP mode. External crystal applications should use the full STOP recovery time, that is, with SSREC cleared.
SIM counter and reset states
External reset has no effect on the SIM counter. (See STOP mode on page 86. for details). The SIM counter is free-running after all reset states, see Active resets from internal sources on page 75 for counter control and internal reset recovery sequences.
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System Integration Module (SIM)
Exception control
Normal, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts
Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents onto the stack and sets the interrupt mask (I-bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7 shows interrupt entry timing, and Figure 9 shows interrupt recovery timing.
MODULE INTERRUPT
I-bit
IAB
DUMMY
SP
SP - 1 PC- 1[7:0]
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDRESS
IDB
DUMMY
PC-1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 7. Interrupt entry Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority,
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System Integration Module (SIM) Exception control
until the latched interrupt is serviced (or the I-bit is cleared). See Figure 8.
FROM RESET
BREAK INTERRUPT? I BIT SET? NO YES
YES
I-BIT SET? NO
IRQ INTERRUPT?
YES
NO (As many interrupts as exist on chip)
STACK CPU REGISTERS. SET I-BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
Figure 8. Interrupt processing
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MODULE INTERRUPT I-BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[7:0]
PC-1[15:8]
OPCODE
OPERAND
R/W
Figure 9. Interrupt recovery Hardware interrupts Processing of a hardware interrupt begins after completion of the current instruction. When the instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I-bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 9 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I-bit) in the condition code register.
SWI instruction
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System Integration Module (SIM) Break interrupts
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 10. Interrupt recognition example
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
Break interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. See Break Module on page 123. The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
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System Integration Module (SIM)
Status flag protection in break mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
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System Integration Module (SIM) Low-power modes
Low-power modes
Executing the STOP/WAIT instruction puts the MCU in a low-power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
WAIT mode
In WAIT mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 11 shows the timing for WAIT mode entry. A module that is active during WAIT mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In WAIT mode, the CPU clocks are inactive. Refer to the WAIT mode subsection of each module to see if the module is active or inactive in WAIT mode. Some modules can be programmed to be active in WAIT mode. WAIT mode can also be exited by a reset or break. A break interrupt during WAIT mode sets the SIM break STOP/WAIT bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is `0', then the computer operating properly (COP) module is enabled and remains active in WAIT mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 11. WAIT mode entry timing Figure 11 and Figure 13 show the timing for WAIT recovery.
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System Integration Module (SIM)
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 12. WAIT recovery from interrupt or break
32 Cycles IAB $6E0B
32 Cycles RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 13. WAIT recovery from internal reset
STOP mode
In STOP mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from STOP mode. Stacking for interrupts begins after the selected STOP recovery time has elapsed. Reset or break also causes an exit from STOP mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP recovery time is selectable using the SSREC bit in the mask option register (MOR). If SSREC is set, STOP recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from STOP mode.
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System Integration Module (SIM) Low-power modes
NOTE:
External crystal applications should use the full STOP recovery time by clearing the SSREC bit.
A break interrupt during STOP mode sets the SIM break STOP/WAIT bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of STOP recovery. It is then used to time the recovery period. Figure 14 shows STOP mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 14. STOP mode entry timing
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 15. STOP mode recovery from interrupt or break
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System Integration Module (SIM)
SIM registers
The SIM has three memory mapped registers. Table 4 shows the mapping of these registers. Table 4. SIM Registers
Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access mode User User User
SIM break status register (SBSR)
The SIM break status register contains a flag to indicate that a break caused an exit from STOP or WAIT mode.
Bit 7 6 5 4 3 2 1 Bit 0
SBSR $FE00
Read:
SBSW R R R R R R Note(1) 0
R = Reserved for factory test 1. Writing a logic `0' clears SBSW.
R
Write: Reset:
Figure 16. SIM break status register (SBSR) SBSW -- SIM Break STOP/WAIT This status bit is useful in applications requiring a return to STOP or WAIT mode after exiting from a break interrupt. SBSW can be cleared by writing a logic `0' to it. Reset clears SBSW. 1 = STOP or WAIT mode was exited by break interrupt 0 = STOP or WAIT mode was not exited by break interrupt
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System Integration Module (SIM) SIM registers
SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN ; See if STOP or WAIT mode was exited by ; break. LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; If RETURNLO is not `0', ; then just decrement low byte. ; Else deal with high byte, too. ; Point to STOP/WAIT opcode. ; Restore H register.
SIM reset status register (SRSR)
This register contains six flags that show the source of the last reset. The SIM reset status register can be cleared by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Bit 7 SRSR $FE01 Read: Write: POR: 1
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
0
0
0
0
0
0
0
= Unimplemented
Figure 17. SIM reset status register (SRSR) POR -- Power-on reset bit 1 = Last reset caused by POR circuit 0 = Read of SRSR
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PIN -- External reset bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer operating properly reset bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal opcode reset bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal address reset bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI -- Low-voltage inhibit reset bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR
SIM break flag control register (SBFCR)
The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Bit 7 SBFCR $FE03 Read:
6
5
4
3
2
1
Bit 0
BCFE
Write: Reset: 0
R
R
R
R
R
R
R
R
= Reserved for factory test
Figure 18. SIM break flag control register (SBFCR) BCFE -- break clear flag enable bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
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Clock Generator Module (CGM) CGM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Phase-locked loop (PLL) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PLL circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . 97 Manual and automatic PLL bandwidth modes . . . . . . . . . . . . . . 97 Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . 100 Base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CGM external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Crystal amplifier input pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . 102 Crystal amplifier output pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . 102 External filter capacitor pin (CGMXFC). . . . . . . . . . . . . . . . . . . . . 102 PLL analog power pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Oscillator enable signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . 103 Crystal output frequency signal (CGMXCLK) . . . . . . . . . . . . . . . . 103 CGM base clock output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . 103 CGM CPU interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 CGM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PLL control register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PLL Bandwidth control register (PBWC). . . . . . . . . . . . . . . . . . . . 107 PLL Programming register (PPG) . . . . . . . . . . . . . . . . . . . . . . . . . 109 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Special modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 CGM during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . 115 Choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Introduction
This section describes the clock generator module (CGM). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system integration module (SIM) derives the system clocks. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1MHz to 8MHz crystals or ceramic resonators. The PLL can generate an 8MHz bus frequency from an 8 MHz or a 4 MHz crystal.
Features
Features of the CGM include the following: * * * * * Phase-locked loop with output frequency in integer multiples of the crystal reference Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition
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Clock Generator Module (CGM) Functional description
Functional description
The CGM consists of three major submodules: * * * Crystal oscillator circuit which generates the constant crystal frequency clock, CGMXCLK. Phase-locked loop (PLL) which generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit; this software-controlled circuit selects either CGMXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock CGMOUT. The SIM derives the system clocks from CGMOUT.
Figure 1 shows the structure of the CGM.
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Clock Generator Module (CGM)
CRYSTAL OSCILLATOR OSC2 CGMXCLK OSC1 CLOCK SELECT CIRCUIT TO SIM, SCI, msCAN CGMOUT TO SIM
/2
A B S*
SIMOSCEN CGMRDV CGMRCLK BCS
*When S = 1, CGMOUT = B
VDDA
CGMXFC
VSS VRS[7:4]
USER MODE PTC3 MONITOR MODE
PHASE DETECTOR
LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR PLL ANALOG
LOCK DETECTOR
BANDWIDTH CONTROL
INTERRUPT CONTROL
CGMINT
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[7:4]
CGMVDV
FREQUENCY DIVIDER
CGMVCLK
Figure 1. CGM block diagram
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Clock Generator Module (CGM) Functional description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PLLF
PLL Control Register (PCTL) PLLIE
1 PLLON BCS 0 ACQ XLD
1
1
1
LOCK
PLL Bandwidth Control Register (PBWC) AUTO PLL Programming Register (PPG) MUL7
0
0
0
MUL6
MUL5
MUL4 VRS7 VRS6 VRS5 VRS4
= Unimplemented
Figure 2. CGM I/O register summary
Crystal oscillator circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock can also feed the OSC1 pin of the crystal oscillator circuit. For this configuration, the external clock should be connected to the OSC1 pin and the OSC2 pin allowed to float.
Phase-locked loop (PLL) circuit
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually.
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Clock Generator Module (CGM)
PLL circuits The PLL consists of the following circuits: * * * * * Voltage-controlled oscillator (VCO) Modulo VCO frequency divider Phase detector Loop filter Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (4.9152MHz) times a linear factor L, or (L)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency fRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV, running at a frequency fRDV = fRCLK. The VCO's output clock, CGMVCLK, running at a frequency fVCLK, is fed back through a programmable modulo divider. The modulo divider reduces the VCO clock by a factor N. The divider's output is the VCO feedback clock, CGMVDV, running at a frequency fVDV = fVCLK/N. (See Programming the PLL on page 99 for more information). The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in Acquisition and tracking modes on page 97. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the
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Clock Generator Module (CGM) Functional description
speed of the lock detector is directly proportional to the final reference frequency fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. Acquisition and tracking modes The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- in acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the resulting VCO frequency is much different from the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. See PLL Bandwidth control register (PBWC) on page 107 Tracking mode -- in tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See Base clock selector circuit on page 100 The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set.
*
Manual and automatic PLL bandwidth modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode is used also to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See PLL Bandwidth control register (PBWC) on page 107 If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See Base clock selector circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and
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the software must take appropriate action, depending on the application. (See Interrupts on page 111 for information and precautions on using interrupts). The following conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (see PLL Bandwidth control register (PBWC) on page 107) is a read-only indicator of the mode of the filter, see Acquisition and tracking modes on page 97. The ACQ bit is set when the VCO frequency is within a certain tolerance TRK and is cleared when the VCO frequency is out with a certain tolerance UNT. (See Acquisition/lock time specifications on page 114). The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance LOCK and is cleared when the VCO frequency is outgrowth a certain tolerance UNL. (See Acquisition/lock time specifications on page 114). CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. (See PLL control register (PCTL) on page 105).
*
* *
*
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX and require fast start-up. The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (see Acquisition/lock time specifications on page 114), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
*
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Clock Generator Module (CGM) Functional description
*
Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGM are disabled.
* * Programming the PLL
The following procedure shows how to program the PLL.
NOTE:
The round function in the following equations means that the real number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES. 2. Calculate the desired VCO frequency (four times the desired bus frequency). f VCLKDES = 4 x f BUDES 3. Choose a practical PLL reference frequency, fRCLK. 4. Select a VCO frequency multiplier, N. f VCLKDES N = round -------------------------f RCLK 5. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. f VCLK = N x f RCLK f BUS = ( f VCLK ) 4 6. Select a VCO linear range multiplier, L. f VCLK L = round ---------------f NOM where fNOM = 4.9152MHz 7. Calculate and verify the adequacy of the VCO programmed center-of-range frequency fVRS. fVRS = (L)fNOM
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8. Verify the choice of N and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application's tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK.
NOTE:
Exceeding the recommended maximum bus frequency or VCO frequency can cause the MCU to "crash".
9. Program the PLL registers accordingly: a. In the upper 4 bits of the PLL programming register (PPG), program the binary equivalent of N. b. In the lower 4 bits of the PLL programming register (PPG), program the binary equivalent of L.
Special programming exceptions
The programming method described in Programming the PLL on page 99, does not account for two possible exceptions -- a value of zero for N or L is meaningless when used in the equations given. To account for these exceptions: * * A zero value for N is interpreted exactly the same as a value of one. A zero value for L disables the PLL and prevents its selection as the source for the base clock. (See Base clock selector circuit on page 100).
Base clock selector circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the
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selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a zero. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock.
CGM external connections
In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 3. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional)
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information. Figure 3 also shows the external components for the PLL: * * Bypass capacitor, CBYP Filter capacitor, CF
Care should be taken with routing in order to minimize signal cross talk and noise. See Acquisition/lock time specifications on page 114 for routing information and more information on the filter capacitor's value and its effects on PLL performance.
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SIMOSCEN
CGMXCLK
OSC1
OSC1
VSSA
CGMXFC CF
VDDA VDD CBYP
RS* RB
X1
C1
C2
*RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data.
Figure 3. CGM external connections
I/O Signals
The following paragraphs describe the CGM I/O signals.
Crystal amplifier input pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
Crystal amplifier output pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
External filter capacitor pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
NOTE:
To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the CF connection.
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Clock Generator Module (CGM) I/O Signals
PLL analog power pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. The pin should be connected to the same voltage potential as the VDD pin.
NOTE:
Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
Oscillator enable signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL.
Crystal output frequency signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and is generated directly from the crystal oscillator circuit. Figure 1 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start-up.
CGM base clock output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output (CGMXCLK) divided by two or the VCO clock (CGMVCLK) divided by two.
CGM CPU interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
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CGM registers
The following registers control and monitor operation of the CGM: * * * PLL control register (PCTL). (See PLL control register (PCTL) on page 105). PLL bandwidth control register (PBWC). (See PLL Bandwidth control register (PBWC) on page 107). PLL programming register (PPG). (See PLL Programming register (PPG) on page 109).
Figure 4 is a summary of the CGM registers.
Bit 7 PCTL $001C PBWC $001D PPG $001E Read: 6 5 4 3 2 1 Bit 0
PLLF PLLIE PLLON LOCK AUTO ACQ XLD BCS
1
1
1
1
Write: Read: Write: Read:
0
0
0
0
MUL7
Write:
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
= Unimplemented
NOTES: 1. When AUTO = 0, PLLIE is forced to logic zero and is read-only. 2. When AUTO = 0, PLLF and LOCK read as logic zero. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4. CGM I/O Register Summary
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Clock Generator Module (CGM) CGM registers
PLL control register (PCTL)
The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit.
Bit 7 6 5 4 3 2 1 Bit 0
PCTL $001C
Read:
PLLF PLLIE PLLON
0 1
1 BCS
0 1
1
1
1
Write: Reset: 0 1 1 1
= Unimplemented
Figure 5. PLL control register (PCTL) PLLIE -- PLL interrupt enable bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as `0'. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF -- PLL interrupt flag bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit is set also. PLLF always reads as `0' when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. The PLLF bit should be cleared by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition
NOTE:
The PLLF bit should not be inadvertently cleared. Any read or read-modify-write operation on the PLL control register clears the PLLF bit.
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PLLON -- PLL on bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See Base clock selector circuit on page 100 Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base clock select bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See Base clock selector circuit on page 100 Reset and the STOP instruction clear the BCS bit. 1 = CGMOUT driven by CGMVCLK/2 0 = CGMOUT driven by CGMXCLK/2
NOTE:
PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See Base clock selector circuit on page 100
PCTL[3:0] -- Unimplemented bits These bits provide no function and always read as `1'.
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Clock Generator Module (CGM) CGM registers
PLL Bandwidth control register (PBWC)
The PLL bandwidth control register does the following: * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode
Bit 7 6 5 4 3 2 1 Bit 0
PBWC $001D
Read:
LOCK AUTO ACQ
0 0
0 XLD
0 0
0
0
0
Write: Reset: 0 0 0 0
= Unimplemented
Figure 7. PLL bandwidth control register (PBWC) AUTO -- Automatic bandwidth control bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), the ACQ bit should be cleared before turning the PLL on. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock indicator bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as `0' and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked
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ACQ -- Acquisition mode bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode XLD -- Crystal loss detect bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit indicates whether the crystal reference frequency is active or not. To check the status of the crystal reference, the following procedure should be followed: 1. Write a `1' to XLD. 2. Wait 4 x N cycles. (N is the VCO frequency multiplier.) 3. Read XLD. 1 = Crystal reference is not active 0 = Crystal reference is active The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as `0'. PBWC[3:0] -- Reserved for test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write zeros to PBWC[3:0] whenever writing to PBWC.
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Clock Generator Module (CGM) CGM registers
PLL Programming register (PPG)
The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO.
Bit 7 6 5 4 3 2 1 Bit 0
PPG $001E
Read:
MUL7
Write: Reset: 0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
Figure 8. PLL Programming register (PPG) MUL[7:4] -- Multiplier select bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. (See PLL circuits on page 96 and Programming the PLL on page 99). A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6. Table 7. VCO frequency multiplier (N) selection
MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 VCO Frequency Multiplier (N) 1 1 2 3
1101 1110 1111
13 14 15
NOTE:
The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1).
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VRS[7:4] -- VCO range select bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency fVRS. (See PLL circuits on page 96, Programming the PLL on page 99, and PLL control register (PCTL) on page 105). 1 = VRS[7:4] cannot be written when the PLLON bit in the PLL control register (PCTL) is set. (See Special programming exceptions on page 100). A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. (See Base clock selector circuit on page 100 and Special programming exceptions on page 100 for more information). Reset initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock.
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Clock Generator Module (CGM) Interrupts
Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as `0'. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency-sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations.
NOTE:
Software can select CGMVCLK/2 as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
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Special modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
WAIT mode
The WAIT instruction does not affect the CGM. Before entering WAIT mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL.
STOP mode
When the STOP instruction executes, the SIM drives the SIMOSCEN signal low, disabling the CGM and holding low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear.
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Clock Generator Module (CGM) CGM during break interrupts
CGM during break interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See System Integration Module (SIM) on page 69. To allow software to clear status bits during a break interrupt, a `1' should be written to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a `0' to the BCFE bit. With BCFE at `0' (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
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Acquisition/lock time specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.
Acquisition/lock time definitions
Typical control systems refer to the acquisition time or lock time as the reaction time of the system, within specified tolerances, to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5% acquisition time tolerance. If a command instructs the system to change from 0Hz to 1MHz, the acquisition time is the time taken for the frequency to reach 1MHz 50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at 1MHz and suffers a -100kHz noise hit, the acquisition time is the time taken to return from 900kHz to 1MHz 5kHz. 5kHz = 5% of the 100kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are as follows: * Acquisition time, tACQ, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance TRK. Acquisition time is based on an initial frequency error, (fDES -
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Clock Generator Module (CGM) Acquisition/lock time specifications
fORIG)/fDES, of not more than 100%. In automatic bandwidth control mode (see Manual and automatic PLL bandwidth modes on page 97), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). * Lock time, tLOCK, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance LOCK. Lock time is based on an initial frequency error, (fDES - fORIG)/fDES, of not more than 100%. In automatic bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). See Manual and automatic PLL bandwidth modes on page 97.
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.
Parametric influences on reaction time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor
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is too large, the PLL may not be able to adjust the voltage in a reasonable time. See Choosing a filter capacitor on page 116. Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.
Choosing a filter capacitor
As described in Parametric influences on reaction time on page 115, the external filter capacitor CF is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to the following equation: V DDA C F = C FACT --------------- f RDV For the value of VDDA, the voltage potential at which the MCU is operating should be used. If the power supply is variable, choose a value near the middle of the range of possible supply values. This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the
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Clock Generator Module (CGM) Acquisition/lock time specifications
PLL may become unstable. Also, always choose a capacitor with a tight tolerance (20% or better) and low dissipation.
Reaction time calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions: * * * * Correct selection of filter capacitor, CF, (see Choosing a filter capacitor on page 116) Room temperature operation Negligible external leakage on CGMXFC Negligible noise
The K factor in the equations is derived from internal PLL parameters. KACQ is the K factor when the PLL is configured in acquisition mode, and KTRK is the K factor when the PLL is configured in tracking mode. See Acquisition and tracking modes on page 97. V DDA 8 t ACQ = --------------- -------------- f RDV K ACQ V DDA 4 t AL = --------------- -------------- f RDV K RTK t LOCK = t ACQ + t AL Note the inverse proportionality between the lock time and the reference frequency. In automatic bandwidth control mode the acquisition and lock times are quantized into units based on the reference frequency. See Manual and automatic PLL bandwidth modes. A certain number of clock cycles, nACQ, is required to ascertain whether the PLL is within the tracking mode entry tolerance TRK, before exiting acquisition mode. Also, a certain number of clock cycles, nTRK, is required to ascertain whether the PLL is within the lock mode entry tolerance LOCK. Therefore, the acquisition time tACQ, is an integer multiple of nACQ/fRDV,
27-cgm
MC68HC08AZ32 Clock Generator Module (CGM) 117
MOTOROLA
Clock Generator Module (CGM)
and the acquisition to lock time tAL, is an integer multiple of nTRK/fRDV. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than tLOCK as calculated above. In manual mode, it is usually necessary to wait considerably longer than tLOCK before selecting the PLL clock (see Base clock selector circuit on page 100), because the factors described in Parametric influences on reaction time on page 115 may slow the lock time considerably.
Table 8. CGM component specifications
Characteristic Crystal load capacitance Crystal fixed capacitance Crystal tuning capacitance Feedback bias resistor Series resistor Filter capacitor Filter capacitor multiply factor Symbol CL Cf C2 RB RS CF CFACT - 0 - - Min - - Typ. - 2 * CL 2 * CL 22M 330k CFACT * (VDDA / fXCLK) 0.0154 F/sV Max - - - - 1M - - F/sV CBYP must provide low AC impedance from f = fXCLK/100 to 100 *fXCLK, so series resistance must be considered Not required Notes Consult crystal mfg. data Consult crystal mfg. data Consult crystal mfg. data
Bypass capacitor
CBYP
-
0.1 F
-
MC68HC08AZ32 118 Clock Generator Module (CGM)
28-cgm
MOTOROLA
Mask Options Mask Options
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Introduction
This section describes the mask options and the two mask option registers. The mask options are hardwired connections specified at the same time as the ROM code, which allow the user to customize the MCU. The options control the enable or disable of the following functions: * * * * * * * Resets caused by the LVI module Power to the LVI module Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) ROM security1 STOP instruction Computer operating properly (COP) module enable EEPROM security
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM data difficult for unauthorized users
1-maskops
MC68HC08AZ32 Mask Options 119
MOTOROLA
Mask Options
Functional description
Bit 7 MORA $001F 6 5 4 3 2 1 Bit 0
Read: LVISTOP ROMSEC LVIRSTD LVIPWRD SSREC Write: Reset:
COPRS R
STOP R
COPD R
R
R
R
R
R
Unaffected by reset
Figure 9. Mask option register A (MORA) LVISTOP -- LVI Stop Mode Enable Bit LVISTOP enables the LVI module in stop mode. See Low-Voltage Inhibit (LVI) on page 149. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode SEC -- ROM security bit SEC enables the ROM security feature. Setting the SEC bit prevents access to the ROM contents. 1 = ROM security enabled 0 = ROM security disabled LVIRSTD -- LVI reset disable bit LVIRSTD disables the reset signal from the LVI module. See Low-Voltage Inhibit (LVI) on page 149. 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD -- LVI power disable bit LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI) on page 149. 1 = LVI module power disabled 0 = LVI module power enabled
MC68HC08AZ32 120 Mask Options
2-maskops
MOTOROLA
Mask Options Functional description
SSREC -- Short stop recovery bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay. 1 = STOP mode recovery after 32 CGMXCLK cycles 0 = STOP mode recovery after 4096 CGMXCLK cycles If using an external crystal oscillator, the SSREC bit should not be set. COPRS -- COP rate select COPRS is similar to COPL (please note that the logic is reversed) as it determines the timeout period for the COP. 1 = COP timeout period is 218 -- 24 CGMXCLK cycles. 0 = COP timeout period is 213 -- 24 CGMXCLK cycles. STOP -- STOP enable bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP disable bit COPD disables the COP module. See Computer Operating Properly Module (COP) on page 143. 1 = COP module disabled 0 = COP module enabled
3-maskops
MC68HC08AZ32 Mask Options 121
MOTOROLA
Mask Options
Bit 7 MORB $003F Read: Write: Reset:
6
5
4
3
2
1
Bit 0
EESEC
Unaffected by reset = Unimplemented
Figure 10. Mask option register B (MORB) EESEC -- EEPROM security enable bit. EESEC enables the EEPROM security function. Setting EESEC prevents program/erase access to locations $8F0 - $8FF of the EEPROM array and to the EEACR/EENVR configuration registers. See MC68HC08AZ32 EEPROM Security on page 45 1 = EEPROM security function enabled 0 = EEPROM security function disabled Extra care should be exercised when selecting mask option registers since other HC08 family parts may have different options. If in doubt, check with your local field applications representative.
MC68HC08AZ32 122 Mask Options
4-maskops
MOTOROLA
Break Module Break Module
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . 125 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 TIM and PIT during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 126 COP during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Break status and control register (BRKSCR) . . . . . . . . . . . . . . . . 127 Break address registers (BRKH and BRKL) . . . . . . . . . . . . . . . . . 128 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Introduction
This section describes the break module. The break module can generate a break interrupt which stops normal program flow at a defined address in order to begin execution of a background program.
1-brk
MC68HC08AZ32 Break Module 123
MOTOROLA
Break Module
Features
Features of the break module include the following: * * * * Accessible I/O registers during the break interrupt CPU-generated break Interrupts Software-generated break interrupts COP disabling during break interrupts
Functional description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a `1' to the BRKA bit in the break status and control register (BRKSCR).
When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 11 shows the structure of the break module.
MC68HC08AZ32 124 Break Module
2-brk
MOTOROLA
Break Module Functional description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
IAB[7:0]
Figure 11. Break module block diagram Table 1. Break I/O register summary
Register Name Bit 7 6 14 6 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1 Bit 0 Addr.
Break Address Register High (BRKH) Bit 15 Break Address Register Low (BRKL) Bit 7
Bit 8 $FE0C Bit 0 $FE0D $FE0E
Break Status/Control Register (BRKSCR) BRKE BRKA = Unimplemented
Flag protection during break interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90, and the Break Interrupts subsection for each module.
3-brk
MC68HC08AZ32 Break Module 125
MOTOROLA
Break Module
CPU during break interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
TIM and PIT during break interrupts
A break interrupt stops the timer counter.
COP during break interrupts
The COP is disabled during a break interrupt when VHI is present on the RST pin.
MC68HC08AZ32 126 Break Module
4-brk
MOTOROLA
Break Module Break module registers
Break module registers
Three registers control and monitor operation of the break module: * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL)
Break status and control register (BRKSCR)
The break status and control register contains break module enable and status bits.
Bit 7 BRKSCR $FE0E Read:
6
5
4
3
2
1
Bit 0
0 BRKE BRKA
0 0
0
0
0
0
0
Write: Reset: 0 0 0 0 0 0
= Unimplemented
Figure 12. Break status and control register (BRKSCR) BRKE -- Break enable bit This read/write bit enables breaks on break address register matches. BRKE is cleared by writing a `0' to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match BRKA -- Break active bit This read/write status and control bit is set when a break address match occurs. Writing a `1' to BRKA generates a break interrupt. BRKA is cleared by writing a `0' to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
5-brk
MC68HC08AZ32 Break Module 127
MOTOROLA
Break Module
Break address registers (BRKH and BRKL) The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Bit 7 BRKH $FE0C Read:
6
5
4
3
2
1
Bit 0
Bit 15
Write: Reset: 0 Bit 7
14
0 6
13
0 5
12
0 4
11
0 3
10
0 2
9
0 1
Bit 8
0 Bit 0
BRKL $FE0D
Read:
Bit 7
Write: Reset: 0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Figure 13. Break address registers (BRKH and BRKL)
MC68HC08AZ32 128 Break Module
6-brk
MOTOROLA
Break Module Low-power modes
Low-power modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
Wait Mode
If enabled, the break module is active in wait mode. The SIM break stop/wait bit (SBSW) in the SIM break status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return address on the stack by subtracting one from it. (See System Integration Module (SIM) on page 69).
Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register states. A break interrupt will cause an exit from stop mode and sets the SBSW bit in the SIM break status register.
7-brk
MC68HC08AZ32 Break Module 129
MOTOROLA
Break Module
MC68HC08AZ32 130 Break Module
8-brk
MOTOROLA
Monitor ROM (MON) Monitor ROM
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Introduction
This section describes the monitor ROM (MON08). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer.
1-mon
MC68HC08AZ32 Monitor ROM (MON) 131
MOTOROLA
Monitor ROM (MON)
Features
Features of the monitor ROM include the following: * * * * * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor ROM and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Up to 28.8K baud communication with host computer Execution of code in RAM or ROM EEPROM programming ROM security
Functional description
The monitor ROM receives and executes commands from a host computer. Figure 1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. While simple monitor commands can access any memory address, the MC68HC08AZ32 has a ROM security feature to prevent external viewing of the contents of ROM. Proper procedures must be followed to verify ROM content. Access to the ROM is denied to unauthorized users of customer specified software with security enabled. See Security on page 141. User mode should be used to verify ROM contents. In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0 retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor.
MC68HC08AZ32 132 Monitor ROM (MON)
2-mon
MOTOROLA
Monitor ROM (MON) Functional description
VDD 68HC08 10 k RST 0.1 F
VHI 10 IRQ
VDDA
VDDA CGMXFC
1 10 F + 3 4 10 F +
MC145407
20 + 18 17 + 10 F 20 pF X1 4.9152 MHz 20 pF 10 F
0.1 F
OSC1 10 M OSC2 VSSA VSS
2
19
DB-25 2 3 7
5 6
16 15 VDD 0.1 F VDD 1 2 6 4 MC68HC125 14 3 5 VDD 10 k A (See NOTE.) B VDD 10 k PTA0 PTC3 VDD 10 k PTC0 PTC1
VDD
7
NOTE: Position A -- Bus clock = CGMXCLK / 4 or CGMVCLK / 4 Position B -- Bus clock = CGMXCLK / 2
Figure 1. Monitor mode circuit
3-mon
MC68HC08AZ32 Monitor ROM (MON) 133
MOTOROLA
Monitor ROM (MON)
Entering monitor mode Table 1 shows the pin conditions for entering monitor mode.
Table 1. Mode selection
PTC0 Pin PTC1 Pin PTA0 Pin PTC3 Pin IRQ Pin Mode CGMOUT Bus Frequency
CGMOUT ------------------------2 CGMOUT ------------------------2
VHI VHI
1 1
0 0
1 1
1 0
Monitor Monitor
CGMXCLK CGMVCLK ---------------------------- or ---------------------------2 2
CGMXCLK
Enter monitor mode by either * * Executing a software interrupt instruction (SWI) or Applying a `0' and then a `1' to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes (see Security on page 141). After the security bytes, the MCU sends a break signal (10 consecutive `0's) to the host computer, indicating that it is ready to receive a command. Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. The COP module is disabled in monitor mode as long as VHI (see 5.0 Volt DC Electrical Characteristics on page 380), is applied to either the IRQ pin or the RST pin. See System Integration Module (SIM) on page 69 for more information on modes of operation.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
MC68HC08AZ32 134 Monitor ROM (MON)
4-mon
MOTOROLA
Monitor ROM (MON) Functional description
Table 2 is a summary of the differences between user mode and monitor mode. Table 2. Mode differences
Functions Modes COP Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
User Monitor
1. If the high voltage (VHI) is removed from the IRQ/VPP pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the mask option register. See 5.0 Volt DC Electrical Characteristics on page 380.
Data format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 2 and Figure 3).
START BIT NEXT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 2. Monitor data format
$A5
START BIT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT STOP BIT
NEXT START BIT
BREAK
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
NEXT START BIT
Figure 3. Sample monitor waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8K baud. Transmit and receive baud rates must be identical.
5-mon
MC68HC08AZ32 Monitor ROM (MON) 135
MOTOROLA
Monitor ROM (MON)
Echoing The monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking, as shown in Figure 4.
SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Figure 4. Read transaction Any result of a command appears after the echo of the last byte of the command.
Break signal
A break signal is a start bit followed by nine low bits. This is shown in Figure 4. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 5. Break transaction Commands The monitor ROM uses the following commands: * * * * * *
MC68HC08AZ32 136 Monitor ROM (MON)
READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
6-mon
MOTOROLA
Monitor ROM (MON) Functional description
Table 3. READ (read memory) command
Description Operand Data returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A
Command sequence
SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Table 4. WRITE (write memory) command
Description Operand Data returned Opcode Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49
Command sequence
SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
ECHO
7-mon
MC68HC08AZ32 Monitor ROM (MON) 137
MOTOROLA
Monitor ROM (MON)
Table 5. IREAD (indexed read) command
Description Operand Data returned Opcode Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A
Command sequence
SENT TO MONITOR IREAD IREAD DATA DATA
ECHO
RESULT
Table 6. IWRITE (indexed write) command
Description Operand Data returned Opcode Write to last address accessed + 1 Specifies single data byte None $19
Command sequence
SENT TO MONITOR IWRITE IWRITE DATA DATA
ECHO
MC68HC08AZ32 138 Monitor ROM (MON)
8-mon
MOTOROLA
Monitor ROM (MON) Functional description
A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64K byte memory map. Table 7. READSP (read stack pointer) command
Description Operand Data returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C
Command sequence
SENT TO MONITOR READSP READSP SP HIGH SP LOW
ECHO
RESULT
Table 8. RUN (run user program) command
Description Operand Data returned Opcode Executes RTI instruction None None $28
Command sequence
SENT TO MONITOR RUN RUN
ECHO
Baud rate
With a 4.9152MHz crystal and the PTC3 pin at `1' during reset, data is transferred between the monitor and host at 4800 baud. If the PTC3 pin is at `0' during reset, the monitor baud rate is 9600. When the CGM output, CGMOUT, is driven by the PLL, the baud rate is determined by
9-mon
MC68HC08AZ32 Monitor ROM (MON) 139
MOTOROLA
Monitor ROM (MON)
the MUL[7:4] bits in the PLL programming register (PPG). Refer to Clock Generator Module (CGM) on page 91. Table 9. Monitor Baud Rate Selection
Monitor Baud Rate 4.9152 MHz 4.194 MHz VCO Frequency Multiplier (N) 1 4800 4096 2 9600 8192 3 14,400 12,288 4 19,200 16,384 5 24,000 20,480 6 28,800 24,576
Later revisions feature a monitor mode which is optimised to operate with either a 4.1952MHz crystal clock source (or multiples of 4.1952MHz) or a 4MHz crystal (or multiples of 4MHz). This supports designs which use the MSCAN module, which is generally clocked from a 4MHz, 8MHz or 16MHz crystal. The table below outlines the available baud rates for a range of crystals and how they can match to a PC baud rate. Table 10
Baud rate Clock freq 32kHz 1MHz 2MHz 4MHz 4.194MHz 4.9152MHz 8MHz 16MHz PTC3=0 57.97 1811.59 3623.19 7246.37 7597.83 8904.35 14492.72 28985.51 PTC3=1 28.98 905.80 1811.59 3623.19 3798.91 4452.17 7246.37 14492.75 Closest PC baud PC PTC3=0 57.6 1800 3600 7200 7680 8861 14400 28800 PTC3=1 28.8 900 1800 3600 3840 4430 7200 14400 Error % PTC3=0 0.64 0.64 0.64 0.64 1.08 0.49 0.64 0.64 PTC3=1 0.63 0.64 0.64 0.64 1.08 0.50 0.64 0.64
Care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure.
MC68HC08AZ32 140 Monitor ROM (MON)
10-mon
MOTOROLA
Monitor ROM (MON) Functional description
Security
A security feature discourages unauthorized reading of ROM locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the byte locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data.
NOTE:
Do not leave locations $FFF6-$FFFD blank. For security reasons, enter data at locations $FFF6-$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all ROM locations and execute code from ROM. Security remains bypassed until a power-on reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. If the reset was not a power-on reset, security remains bypassed regardless of the data that the host sends. If the received bytes do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading ROM locations returns undefined data, and trying to execute code from ROM causes an illegal address reset. After the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends the eight security bytes.
11-mon
MC68HC08AZ32 Monitor ROM (MON) 141
MOTOROLA
Monitor ROM (MON)
V DD 4096 + 32 CGMXCLK CYCLES RST 24 CGMXCLK CYCLES PA7 256 CGMXCLK CYCLES (ONE BIT TIME) Command 1 Byte 2 Echo Byte 8 Echo 2 Break 4 1 Command Echo 12-mon Byte 1 Byte 2 Byte 8 1
FROM HOST
PA0 1 Byte 1 Echo FROM MCU 4
NOTE: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte.
Figure 6. Monitor mode entry timing
MC68HC08AZ32 142 Monitor ROM (MON)
MOTOROLA
Computer Operating Properly Module (COP) COP
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 STOP instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 COPCTL write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 COPD (COP disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 COP Control register (COPCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 COP module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 148
Introduction
This section describes the computer operating properly (COP) module, a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. COP resets can be prevented by periodically clearing the COP counter.
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Computer Operating Properly Module (COP)
Functional description
Figure 1 shows the structure of the COP module.
CGMXCLK
12-BIT COP PRESCALER CLEAR ALL BITS CLEAR BITS 12-4
RESET RESET STATUS REGISTER
STOP INSTRUCTION INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COPMODULE
COPEN (FROM SIM) COPD (FROM MOR) RESET COPCTL WRITE 6-BIT COP COUNTER
CLEAR COP COUNTER
NOTE:1. See Active resets from internal sources on page 75.
Figure 1. COP block diagram
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Computer Operating Properly Module (COP) Functional description
Table 1. COP I/O register summary
Register Name COP Control Register (COPCTL) Bit 7 6 5 4 3 2 1 Bit 0 Addr. $FFFF
The COP counter is a free-running 6-bit counter preceded by a12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 213 - 24, or 218 - 24CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS in MORA. When COPRS = 1, a 4.9152 MHz crystal, gives a COP timeout period of 53.3ms. Writing any value to location $FFFF before overflow occurs prevents a COP reset by clearing the COP counter and stages 5 through 12 of the prescaler. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status register (SRSR). See SIM reset status register (SRSR) on page 89.The COP should be cleared immediately before entering or after exiting STOP mode to assure a full COP timeout period. A CPU interrupt routine can be used to clear the COP.
NOTE:
COP clearing instructions should be placed in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
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Computer Operating Properly Module (COP)
I/O Signals
The following paragraphs describe the signals shown in Figure 1.
CGMXCLK
CGMXCLK is the crystal oscillator output signal. The CGMXCLK frequency is equal to the crystal frequency.
STOP instruction
The STOP instruction clears the COP prescaler.
COPCTL write
Writing any value to the COP control register (COPCTL) (see COP Control register (COPCTL) on page 147), clears the COP counter and clears bits 12 - 4 of the SIM counter. Reading the COP control register returns the reset vector.
Power-on reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after power-up.
Internal reset
An internal reset clears the COP prescaler and the COP counter.
Reset vector fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler.
COPD (COP disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the mask option register (MORA). See Mask Options on page 119
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Computer Operating Properly Module (COP) COP Control register (COPCTL)
COP Control register (COPCTL)
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Bit 7 COPCTL $FFFF Read: Write: Reset: 6 5 4 3 2 1 Bit 0
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 2. COP control register (COPCTL)
Interrupts
The COP does not generate CPU interrupt requests.
Monitor mode
The COP is disabled in monitor mode when VHI is present on the IRQ pin or on the RST pin.
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Computer Operating Properly Module (COP)
Low-power modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
WAIT mode
The COP continues to operate during WAIT mode. To prevent a COP reset during WAIT mode, the COP counter should be cleared periodically in a CPU interrupt routine.
STOP mode
STOP mode turns off the CGMXCLK input to the COP and clears the COP prescaler. The COP should be serviced immediately before entering or after exiting STOP mode to ensure a full COP timeout period after entering or exiting STOP mode. The STOP bit in the mask option register (MOR) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, the STOP instruction should be disabled by programming the STOP bit to `0'.
COP module during break interrupts
The COP is disabled during a break interrupt when VHI is present on the RST pin.
MC68HC08AZ32 148 Computer Operating Properly Module (COP)
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Low-Voltage Inhibit (LVI) LVI
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Polled LVI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 False reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LVI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Introduction
This section describes the low-voltage inhibit module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.
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Low-Voltage Inhibit (LVI)
Features
Features of the LVI module include the following: * * * Programmable LVI reset Programmable power consumption Digital filtering of VDD pin level
NOTE:
If a low voltage interrupt (LVI) occurs during programming of EEPROM memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. It is the responsibility of the user to ensure that in the event of an LVI any addresses being programmed receive specification programming conditions.
Functional description
Figure 1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, LVITRIPF, and remains at or below that level for 9 or more consecutive CPU cycles. Note that short VDD spikes may not trip the LVI. It is the user's responsibility to ensure a clean VDD signal within the specified operating voltage range if normal microcontroller operation is to be guaranteed. LVIPWRD and LVIRSTD are mask options. See Mask Options on page 119. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
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Low-Voltage Inhibit (LVI) Functional description
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
V DD
LVIPWRD (FROM MOR) CPU CLOCK LOW VDD DETECTOR V DD > LVITRIP = 0 V DD < LVITRIP = 1 VDD DIGITAL FILTER (FROM MOR) LVIRSTD LVI RESET
ANLGTRIP
LVIOUT
Figure 1. LVI module block diagram Table 1. LVI I/O register summary
Register Name Bit 7 6 5 4 3 2 1 Bit 0 Addr. $FE0F = Unimplemented
LVI Status Register (LVISR) LVIOUT
Polled LVI operation
In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by polling the LVIOUT bit. In the mask option register, the LVIPWRD and LVIRSTD bits must be at `0' to enable the LVI module and to enable the LVI resets. Also, the LVIPRWD bit must be at `0' to enable the LVI module, and the LVIRSTD bit must be at `1' to disable LVI resets.
Forced reset operation
In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for 9 or more consecutive CPU cycles. In the mask option register, the LVIPWRD and LVIRSTD bits must be at `0' to enable the LVI module and to enable LVI resets.
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Low-Voltage Inhibit (LVI)
False reset protection The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI module to reset the MCU,VDD must remain at or below the LVITRIPF level for 9 or more consecutive CPU cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset.
LVI Status Register (LVISR)
The LVI status register flags VDD voltages below the LVITRIPF level.
Bit 7 LVISR $FE0F Read: LVIOUT Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
0
0
0
0
0
0
0
= Unimplemented
Figure 2. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when VDD falls below the LVITRIPF voltage for 32-40 CGMXCLK cycles. (See Table 2). Reset clears the LVIOUT bit. Table 2. LVIOUT bit indication
VDD at level: VDD > LVITRIPR VDD < LVITRIPF VDD < LVITRIPF VDD < LVITRIPF LVITRIPF < VDD < LVITRIPR for number of CGMXCLK cycles: ANY < 32 CGMXCLK cycles between 32 & 40 CGMXCLK cycles > 40 CGMXCLK cycles ANY LVIOUT 0 0 0 or 1 1 Previous Value
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Low-Voltage Inhibit (LVI) LVI interrupts
LVI interrupts
The LVI module does not generate interrupt requests.
Low-power modes
The WAIT instruction puts the MCU in low-power-consumption standby mode.
WAIT mode
When the LVIPWRD mask option is programmed to `0', the LVI module is active after a WAIT instruction. When the LVIRSTD mask option is programmed to `0', the LVI module can generate a reset and bring the MCU out of WAIT mode.
Stop Mode
With LVISTOP=1 and LVIPWRD=0 in the MORA register, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter to generate a reset and bring the MCU out of stop. With the LVIPWRD bit in the MORA register at a logic 0 and the LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP instruction. Note that the LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application VDD voltage collapsing completely to an unsafe level. Is is not intended that users operate the microcontroller at lower than the specified operating voltage, VDD.
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Low-Voltage Inhibit (LVI)
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External Interrupt Module (IRQ) IRQ
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 IRQ module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 160 IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . . . . 160
Introduction
The IRQ module provides the nonmaskable interrupt input.
Features
Features of the IRQ module include the following: * * * * * Dedicated external interrupt pins (IRQ) IRQ interrupt control bit Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge
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External Interrupt Module (IRQ)
Functional description
A `0' applied to any of the external interrupt pins can latch a CPU interrupt request. Figure 3 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following occurs: * Vector fetch -- a vector fetch automatically generates an interrupt acknowledge signal which clears the latch that caused the vector fetch. Software clear -- software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR). Writing a `1' to the ACK1 bit clears the IRQ latch. Reset -- a reset automatically clears the interrupt latch.
*
*
INTERNAL ADDRESS BUS ACK1
VECTOR FETCH DECODER
TO CPU FOR BIL/BIH INSTRUCTIONS
VDD D IRQ CLR Q SYNCHRONIZER
IRQF IRQ INTERRUPT REQUEST
CK IRQ LATCH
IMASK1
MODE1 HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 3. IRQ module block diagram All of the external interrupt pins are falling-edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ pin.
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External Interrupt Module (IRQ) Functional description
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to `1'
The vector fetch or software clear may occur before or after the interrupt pin returns to `1'. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODEx1control bit, thereby clearing the interrupt even if the pin stays low. Table 1. IRQ I/O register summary
Register Name IRQ Status/Control Register (ISCR) Bit 7 6 5 4 3 IRQF 2 1 Bit 0 Addr.
ACK1 IMASK1 MODE1 $001A
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. See Figure 4
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External Interrupt Module (IRQ)
.
FROM RESET
YES
I BIT SET?
NO
INTERRUPT?
YES
NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION?
YES
NO
RTI INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO EXECUTE INSTRUCTION.
Figure 4. IRQ interrupt flowchart
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External Interrupt Module (IRQ) Functional description
IRQ pin
A `0' on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE1 set, both of the following actions must occur to clear the IRQ latch: * Vector fetch or software clear -- a vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a `1' to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK1 bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to `1' -- as long as the IRQ pin is at `0', the IRQ latch remains set.
*
The vector fetch or software clear and the return of the IRQ pin to `1' may occur in any order. The interrupt request remains pending as long as the IRQ pin is at `0'. A reset will clear the latch and the MODEx control bit, thereby clearing the interrupt even if the pin stays low. If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK1 bit, which makes it useful in applications where polling is preferred. The BIH or BIL instruction is used to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, false interrupts can be avoided by masking interrupt requests in the interrupt routine.
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External Interrupt Module (IRQ)
IRQ module during break interrupts
The system integration module (SIM) controls whether the IRQ interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latches during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear the IRQ latch during a break interrupt, a `1' is written to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, a `0' is written to the BCFE bit. With BCFE at `0' (its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
IRQ status and control register (ISCR)
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR performs the following functions: * * * * Indicates the state of the IRQ interrupt flag Clears the IRQ interrupt latch Masks IRQ interrupt requests Controls triggering sensitivity of the IRQ interrupt pin
Bit 7 ISCR $001A Read: Write: Reset: 0 0 0 0 0 6 5 4 3 2 1 Bit 0
IRQF
0 IMASK1 MODE1 ACK1
0 0 0
= Unimplemented
Figure 5. IRQ status and control register (ISCR)
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External Interrupt Module (IRQ) IRQ status and control register (ISCR)
IRQF -- IRQ flag This read-only status bit is high when the IRQ interrupt is pending. 1 = Interrupt pending 0 = Interrupt not pending ACK1 -- IRQ interrupt request acknowledge bit Writing a `1' to this write-only bit clears the IRQ latch. ACK1 always reads as `0'. Reset clears ACK1. IMASK1 -- IRQ Interrupt mask bit Writing a `1' to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE1 -- IRQ edge/level select bit This read/write bit controls the triggering sensitivity of the IRQ/VPP pin. Reset clears MODE1. 1 = Interrupt requests on falling edges and low levels 0 = Interrupt requests on falling edges only
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External Interrupt Module (IRQ)
MC68HC08AZ32 162 External Interrupt Module (IRQ)
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Serial Communications Interface Module (SCI) SCI
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SCI during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 180 I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PTE0/TxD (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PTE1/RxD (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SCI control register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SCI control register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SCI status register 1 (SCS1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SCI status register 2 (SCS2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SCI data register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SCI baud rate register (SCBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Introduction
This section describes the serial communications interface module, which allows high-speed asynchronous communications with peripheral devices and other MCUs.
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Serial Communications Interface Module (SCI)
Features
Features of the SCI module include the following: * * * * * * * * Full duplex operation Standard mark/space non-return-to-zero (NRZ) format 32 programmable baud rates Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Programmable transmitter output polarity Two receiver wake-up methods: - Idle line wake-up - Address mark wake-up * Interrupt-driven operation with eight interrupt flags: - Transmitter empty - Transmission complete - Receiver full - Idle receiver input - Receiver overrun - Noise error - Framing error - Parity error * * * Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
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Serial Communications Interface Module (SCI) Functional description
Functional description
Figure 1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Table 1. SCI I/O register summary
Register Name Bit 7 6 5 4 M ILIE R IDLE 3 WAKE TE ORIE OR 2 ILTY RE NEIE NF 1 PEN RWU FEIE FE BKF Bit 0 Addr.
SCI Control Register 1 (SCC1) LOOPS ENSCI TXINV SCI Control Register 2 (SCC2) SCTIE SCI Control Register 3 (SCC3) R8 TCIE T8 TC SCRIE R SCRF
PTY $0013 SBK $0014 PEIE $0015 PE $0016
SCI Status Register 1 (SCS1) SCTE SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR)
RPF $0017 $0018
SCP1
SCP0
SCR2 SCR1 SCR0 $0019
= Unimplemented
R
= Reserved
Data format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 6.
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Serial Communications Interface Module (SCI)
8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT
POSSIBLE PARITY BIT BIT 7 STOP BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
NEXT START BIT
9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
POSSIBLE PARITY BIT BIT 8 STOP BIT
NEXT START BIT
Figure 6. SCI data formats
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Serial Communications Interface Module (SCI) Functional description
INTERNAL BUS
TRANSMITTER INTERRUPT CONTROL
SCI DATA REGISTER RECEIVE SHIFT REGISTER
SCI DATA REGISTER RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TRANSMIT SHIFT REGISTER
PTE1/RxD
PTE2/TxD
TXINV SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKE-UP CONTROL RECEIVE CONTROL FLAG CONTROL M WAKE ILTY CGMXCLK /4 PREBAUD RATE SCALER GENERATOR PEN PTY ENSCI TRANSMIT CONTROL ORIE NEIE FEIE PEIE
R8 T8
ENSCI
BKF RPF
/16
DATA SELECTION CONTROL
Figure 1. SCI module block diagram
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Serial Communications Interface Module (SCI)
Transmitter Figure 2 shows the structure of the SCI transmitter.
INTERNAL BUS
/4
CGMXCLK SCP1 SCP0 SCR1 SCR2
PREBAUD SCALER DIVIDER
/ 16
SCI DATA REGISTER
STOP
11-BIT TRANSMIT SHIFT REGISTER 8 MSB 7 6 5 4 3 2 1 0
H
TRANSMITTER CPU INTERRUPT REQUEST
START L
PTE2/TxD
SCR0
TXINV
RESERVED SERVICE REQUEST
LOAD FROM SCDR
M PEN PTY PARITY GENERATION
SHIFT ENABLE
T8 R R SCTIE SCTE R SCTE SCTIE TC TCIE
TRANSMITTER CONTROL LOGIC
SCTE
PREAMBLE (ALL ONES)
SBK LOOPS
SCTIE TC TCIE
ENSCI TE
Figure 2. SCI transmitter Character length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8).
MC68HC08AZ32 168 Serial Communications Interface Module (SCI)
BREAK (ALL ZEROS)
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Serial Communications Interface Module (SCI) Functional description
Character transmission During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a `1' to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a `1' to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of `1's. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A `0' start bit automatically goes into the least significant bit position of the transmit shift register. A `1' STOP bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the PTE0/TxD pin goes to the idle condition, `1'. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins.
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Serial Communications Interface Module (SCI)
Table 2. SCI transmitter I/O register summary
Register Name Bit 7 6 5 4 M ILIE R IDLE 3 WAKE TE ORIE OR 2 ILTY RE NEIE NF 1 PEN RWU FEIE FE Bit 0 Addr.
SCI Control Register 1 (SCC1)LOOPS ENSCI TXINV SCI Control Register 2 (SCC2) SCTIE TCIE SCRIE SCI Control Register 3 (SCC3) R8 T8 TC R SCRF
PTY $0013 SBK $0014 PEIE $0015 PE $0016 $0018
SCI Status Register 1 (SCS1) SCTE SCI Data Register (SCDR) SCI Baud Rate Register (SCBR)
SCP1
SCP0
SCR2 SCR1 SCR0 $0019
= Unimplemented
R
= Reserved
Break characters Writing a `1' to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all `0's and has no start, STOP, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at `1', transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one `1'. The automatic `1' at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by 8 or 9 `0' data bits and a `0' where the STOP bit should be. Receiving a break character has the following effects on SCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the SCI receiver full bit (SCRF) in SCS1 Clears the SCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
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Serial Communications Interface Module (SCI) Functional description
Idle characters An idle character contains all `1's and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the PTE2/TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted.
NOTE:
When queueing an idle character, return the TE bit to `1' before the stop bit of the current character shifts out to the PTE0/TxD pin. Setting TE after the stop bit appears on PTE0/TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit is when the SCTE bit becomes set and just before writing the next byte to the SCDR.
Inversion of transmitted output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at `1'. See SCI control register 1 (SCC1) on page 181. Transmitter interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: * SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.
*
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Serial Communications Interface Module (SCI)
Receiver Figure 3 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1 SCP1 SCP0 SCR2 SCR0 START L RWU STOP PREBAUD SCALER DIVIDER PTE1/RxD SCI DATA REGISTER
/4
CGMXCLK
/ 16
DATA RECOVERY
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0
H ALL ONES
ERROR CPU INTERRUPT REQUEST RESERVED SERVICE REQUEST CPU INTERRUPT REQUEST
RPF
M WAKE ILTY PEN PTY WAKE-UP LOGIC PARITY CHECKING IDLE ILIE R SCRF SCRIE R SCRF SCRIE R OR ORIE NF NEIE FE FEIE PE PEIE
MSB
BKF
ALL ZEROS
SCRF IDLE
R8
ILIE
SCRIE
R OR ORIE NF NEIE FE FEIE PE PEIE
Figure 3. SCI receiver block diagram
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Serial Communications Interface Module (SCI) Functional description
Table 3. SCI receiver I/O register summary
Register name Bit 7 6 5 4 M ILIE R IDLE 3 WAKE TE ORIE OR 2 ILTY RE NEIE NF 1 PEN RWU FEIE FE BKF Bit 0 Addr.
SCI control register 1 (SCC1)LOOPS ENSCI TXINV SCI control register 2 (SCC2) SCTIE TCIE SCRIE SCI control register 3 (SCC3) R8 T8 TC R SCRF
PTY $0013 SBK $0014 PEIE $0015 PE $0016
SCI status register 1 (SCS1) SCTE SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR)
RPF $0017 $0018
SCP1 SCP0
SCR2 SCR1 SCR0 $0019
= Unimplemented
R
= Reserved
Character length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). Character reception During an SCI reception, the receive shift register shifts characters in from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request.
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Serial Communications Interface Module (SCI)
Data sampling The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 4): * * After every start bit After the receiver detects a data bit change from `1' to `0' (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid `1' and the majority of the next RT8, RT9, and RT10 samples returns a valid `0').
START BIT PTE1/RxD
LSB
SAMPLES
START BIT QUALIFICATION
START BIT DATA VERIFICATION SAMPLING
RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT16 RT1 RT2 RT3 RT CLOCK STATE RT CLOCK RESET RT4 12-sci
Figure 4. Receiver data sampling To locate the start bit, data recovery logic does an asynchronous search for a `0' preceded by three `1's. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
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Serial Communications Interface Module (SCI) Functional description
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 4 summarizes the results of the start bit verification samples. Table 4. Start bit verification
RT3, RT5, and RT7 samples 000 001 010 011 100 101 110 111 Start bit verification Yes Yes Yes No Yes No No No Noise flag 0 1 1 0 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 5 summarizes the results of the data bit samples.
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Serial Communications Interface Module (SCI)
Table 5. Data bit recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data bit determination 0 0 0 1 0 1 1 1 Noise flag 0 1 1 1 1 1 1 0
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are `1's following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 6 summarizes the results of the stop bit samples. Table 6. Stop bit recovery
RT8, RT9, and RT10 samples 000 001 010 011 100 101 110 111 Framing error flag 1 1 1 0 1 0 0 0 noise flag 0 1 1 1 1 1 1 0
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Serial Communications Interface Module (SCI) Functional description
Framing errors If the data recovery logic does not detect a `1' where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. The FE flag is set at the same time that the SCRF bit is set. A break character that has no stop bit also sets the FE bit. Receiver wake-up So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wake-up bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTE1/RxD pin can bring the receiver out of the standby state: * Address mark -- An address mark is a `1' in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. Idle input line condition -- When the WAKE bit is clear, an idle character on the PTE1/RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting `1's as idle character bits after the start bit or after the stop bit.
*
NOTE:
Clearing the WAKE bit after the PTE1/RxD pin has been idle may cause the receiver to wake up immediately.
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MC68HC08AZ32 Serial Communications Interface Module (SCI) 177
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Serial Communications Interface Module (SCI)
Receiver interrupts The following sources can generate CPU interrupt requests from the SCI receiver: * SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive `1's shifted in from the PTE1/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests.
*
Error interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. Noise flag (NF) -- The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) -- The FE bit in SCS1 is set when a `0' occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests.
*
*
*
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Serial Communications Interface Module (SCI) Low-power modes
Low-power modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
Wait mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.
STOP mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data.
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Serial Communications Interface Module (SCI)
SCI during break module interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during interrupts generated by the break module. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear status bits during a break interrupt, write a `1' to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a `0' to the BCFE bit. With BCFE at 0 0 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at `0'. After the break, doing the second step clears the status bit.
I/O signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are: * * PTE0/TxD (transmit data) PTE0/TxD -- Transmit data PTE1/RxD -- Receive data
The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in data direction register E (DDRE). The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE).
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PTE1/RxD (receive data)
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Serial Communications Interface Module (SCI) I/O registers
I/O registers
The following I/O registers control and monitor SCI operation: * * * * * * * SCI control register 1 (SCC1) SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR)
SCI control register 1 does the following: * * * * * * * * Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wake-up method Controls idle character detection Enables parity function Controls parity type
Bit 7 6 5 4 3 2 1 Bit 0
SCC1 $0013
Read:
LOOPS
Write: Reset: 0
ENSCI
0
TXINV
0
M
0
WAKE
0
ILTY
0
PEN
0
PTY
0
Figure 5. SCI control register 1 (SCC1)
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Serial Communications Interface Module (SCI)
LOOPS -- Loop mode select bit This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable SCI bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV -- Transmit inversion bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits.
M -- Mode (character length) bit This read/write bit determines whether SCI characters are 8 or 9 bits long (see Table 7). The ninth bit can serve as an extra stop bit, as a receiver wake-up signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters
MC68HC08AZ32 182 Serial Communications Interface Module (SCI)
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MOTOROLA
Serial Communications Interface Module (SCI) I/O registers
WAKE -- wake-up condition bit This read/write bit determines which condition wakes up the SCI: a `1' (address mark) in the most significant bit position of a received character or an idle condition on the PTE1/RxD pin. Reset clears the WAKE bit. 1 = Address mark wake-up 0 = Idle line wake-up ILTY -- Idle line type bit This read/write bit determines when the SCI starts counting `1's as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of `1's preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity enable bit This read/write bit enables the SCI parity function (see Table 7). When enabled, the parity function inserts a parity bit in the most significant bit position (seeFigure 6). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY -- Parity bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity (see Table 7). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity
NOTE:
Changing the PTY bit in the middle of a transmission or reception can generate a parity error.
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Serial Communications Interface Module (SCI)
Table 7. Character format selection
Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start bits 1 1 1 1 1 1 Data bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd STOP bits 1 1 1 1 1 1 Character length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits
SCI Control Register 2 (SCC2)
SCI control register 2 does the following: * Enables the following CPU interrupt requests: - Enables the SCTE bit to generate transmitter CPU interrupt requests - Enables the TC bit to generate transmitter CPU interrupt requests - Enables the SCRF bit to generate receiver CPU interrupt requests - Enables the IDLE bit to generate receiver CPU interrupt requests * * * * Enables the transmitter Enables the receiver Enables SCI wake-up Transmits SCI break characters
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MOTOROLA
Serial Communications Interface Module (SCI) I/O registers
Bit 7 SCC2 $0014 Read:
6
5
4
3
2
1
Bit 0
SCTIE
Write: Reset: 0
TCIE
0
SCRIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
Figure 6. SCI control register 2 (SCC2) SCTIE -- SCI transmit interrupt enable bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission complete interrupt enable bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE -- SCI receive interrupt enable bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt
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MC68HC08AZ32 Serial Communications Interface Module (SCI) 185
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Serial Communications Interface Module (SCI)
ILIE -- Idle line interrupt enable bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE -- Transmitter enable bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 `1's from the transmit shift register to the PTE2/TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the PTE0/TxD returns to the idle condition ('1'). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1.
RE -- Receiver enable bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1.
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MOTOROLA
Serial Communications Interface Module (SCI) I/O registers
RWU -- Receiver wake-up bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send break bit Setting and then clearing this read/write bit transmits a break character followed by a `1'. The `1' after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no `1's between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK too early causes the SCI to send a break character instead of a preamble.
SCI control register 3 (SCC3)
SCI control register 3 does the following: * * Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables the following interrupts: - Receiver overrun interrupts - Noise error interrupts - Framing error interrupts - Parity error interrupts
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MC68HC08AZ32 Serial Communications Interface Module (SCI) 187
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Serial Communications Interface Module (SCI)
Bit 7 SCC3 $0015 Read: Write: Reset: U
6
5
4
3
2
1
Bit 0
R8 T8
U
R
0
R
0
ORIE
0
NEIE
0
FEIE
0
PEIE
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 7. SCI control register 3 (SCC3) R8 -- Received bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. ORIE -- Receiver overrun interrupt enable bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver noise error interrupt enable bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled. 0 = SCI error CPU interrupt requests from NE bit disabled
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MOTOROLA
Serial Communications Interface Module (SCI) I/O registers
FEIE -- Receiver framing error interrupt enable bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver parity error interrupt enable bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. (see SCI status register 1 (SCS1) on page 189). Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled
SCI status register 1 (SCS1)
SCI status register 1 contains flags to signal the following conditions: * * * * * * * * Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error
Bit 7 6 5 4 3 2 1 Bit 0
SCS1 $0016
Read: Write: Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
= Unimplemented
Figure 8. SCI status register 1 (SCS1)
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SCTE -- SCI transmitter empty bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission complete bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- SCI receiver full bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver idle bit This clearable, read-only bit is set when 10 or 11 consecutive `1's appear on the receiver input. IDLE generates an SCI receive CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the
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Serial Communications Interface Module (SCI) I/O registers
IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR -- Receiver overrun bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 9 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF -- Receiver noise flag bit This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected
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NORMALFLAGCLEARINGSEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR (BYTE 3) BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR (BYTE 3) SCRF = 0 OR = 0
BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR (BYTE 1)
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR (BYTE 2)
BYTE 3
DELAYEDFLAGCLEARINGSEQUENCE SCRF = 1 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 OR = 1 BYTE 3
BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR (BYTE 1)
Figure 9. Flag clearing sequence FE -- Receiver framing error bit This clearable, read-only bit is set when a logic is accepted as the STOP bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE -- Receiver parity error bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected
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Serial Communications Interface Module (SCI) I/O registers
SCI status register 2 (SCS2)
SCI status register 2 contains flags to signal the following conditions: * * Break character detected Incoming data
Bit 7 6 5 4 3 2 1 Bit 0
SCS2 $0017
Read: Write: Reset: 0 0 0 0 0 0
BKF
RPF
0
0
= Unimplemented
Figure 10. SCI status register 2 (SCS2) BKF -- Break flag bit This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after `1's again appear on the PTE1/RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF -- Reception in progress flag bit This read-only bit is set when the receiver detects a `0' during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering STOP mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress
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SCI data register (SCDR) The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register.
Bit 7 SCDR $0018 Read: Write: Reset: 6 5 4 3 2 1 Bit 0
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
Unaffected by reset
Figure 11. SCI data register (SCDR) R7/T7-R0/T0 -- Receive/Transmit data bits Reading address $0018 accesses the read-only received data bits, R7-R0. Writing to address $0018 writes the data to be transmitted, T7-T0. Reset has no effect on the SCI data register.
SCI baud rate register (SCBR)
The baud rate register selects the baud rate for both the receiver and the transmitter.
Bit 7 6 5 4 3 2 1 Bit 0
SCBR $0019
Read:
SCP1
Write: Reset: 0 0 0
SCP0
0 0
SCR2
0
SCR1
0
SCR0
0
= Unimplemented
Figure 12. SCI Baud Rate Register (SCBR) SCP1 and SCP0 -- SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 8. Reset clears SCP1 and SCP0.
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Serial Communications Interface Module (SCI) I/O registers
Table 8. SCI baud rate prescaling
SCP1:0 00 01 10 11 Prescaler Divisor (PD) 1 3 4 13
SCR2-SCR0 -- SCI baud rate select bits These read/write bits select the SCI baud rate divisor as shown in Table 9. Reset clears SCR2-SCR0. Table 9. SCI baud rate selection
SCR2:1:0 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128
Use the following formula to calculate the SCI baud rate: f XCLK Baud rate = ---------------------------------64 x PD x BD where: fXCLK = clock frequency PD = prescaler divisor BD = baud rate divisor Table 10 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal.
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Table 10. SCI baud rate selection examples
SCP1:0 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR2:1:0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud rate divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud rate (fXCLK = 4.9152 MHz) 76,800 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46
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Serial Peripheral Interface Module (SPI) SPI
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Pin name conventions and I/O register addresses . . . . . . . . . . . . . . 199 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . 205 Transmission format when CPHA = `0' . . . . . . . . . . . . . . . . . . . . . 205 Transmission format when CPHA = `1' . . . . . . . . . . . . . . . . . . . . . 207 Transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SPI during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 MISO (Master in/Slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 MOSI (Master out/Slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 SPSCK (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 SS (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 VSS (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SPI control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SPI status and control register (SPSCR) . . . . . . . . . . . . . . . . . . . 226 SPI data register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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Introduction
This section describes the serial peripheral interface module (SPI, Version C), which allows full-duplex, synchronous, serial communications with peripheral devices.
Features
Features of the SPI module include the following: * * * * * * * Full-duplex operation Master and slave modes Double-buffered operation with separate transmit and receive registers Four master mode frequencies (maximum = bus frequency / 2) Maximum slave mode frequency = bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts with CPU service: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) * * * * Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired-OR mode I2C (inter-integrated circuit) compatibility
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Serial Peripheral Interface Module (SPI) Pin name conventions and I/O register addresses
Pin name conventions and I/O register addresses
The text that follows describes both SPI1 and SPI2. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), VSS (clock ground), MOSI (master out slave in), and MISO (master in slave out). The two SPIs share eight I/O pins with two parallel I/O ports. The full names of the SPI I/O pins are as follows: Table 1. Pin name conventions
SPI Generic Pin Names: Full SPI Pin Names: SPI MISO PTE5/MISO MOSI PTE6/MOSI SS PTE4/SS SCK PTE7/SPSCK VSS CGND
Table 2. I/O register addresses
Register name SPI Control Register (SPICR) SPI Status and Control Register (SPISCR) SPI Data Register (SPIDR) Register address $0010 $0011 $0012
The generic pins names appear in the text that follows.
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Functional description
Figure 1 summarizes the SPI I/O registers and Figure 2 show the structure of the SPI module.
Register name SPI Control Register (SPCR) Write: Reset: 0 0 1 OVRF R 0 R5 T5 0 MODF R 0 R4 T4 1 SPTE MODFEN SPR1 SPR0 R 1 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 0 0 R/W Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Bit 7 6 5 4 3 2 1 Bit 0
SPI Status and Control Register Read: SPRF ERRIE (SPSCR) Write: R Reset: Read: SPI Data Register (SPDR) Write: Reset: R T7 T6 0 R7 0 R6
Unaffected by reset = Reserved
Figure 1. SPI I/O register summary
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Serial Peripheral Interface Module (SPI) Functional description
INTERNAL BUS
TRANSMIT DATA REGISTER CGMOUT / 2 (FROM SIM) 7 6
SHIFT REGISTER 5 4 3 2 1 0 MISO
CLOCK DIVIDER
/2 /8 / 32 / 128
CLOCK SELECT
MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS
SPMSTR
SPE
SPR1
SPR0
SPMSTR
CPHA
CPOL
MODFEN TRANSMITTER CPU INTERRUPT REQUEST SPI CONTROL RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE SPTIE SPRIE
SPWOM
SPE SPRF SPTE OVRF MODF
Figure 2. SPI module block diagram The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt-driven. The following paragraphs describe the operation of the SPI module.
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Master mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE:
The SPI modules should be configured as master and slave before they are enabled. Also, the master SPI should be enabled before the slave SPI. Similarly, Disable the slave SPI should be disabled before disabling the master SPI. See SPI control register (SPCR) on page 223.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. See Figure 3. The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. See SPI status and control register (SPSCR) on page 226. Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with
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Serial Peripheral Interface Module (SPI) Functional description
SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTIE bit.
MASTER MCU
SLAVE MCU
SHIFT REGISTER
MISO
MISO
MOSI
MOSI
SHIFT REGISTER
SPSCK BAUD RATE GENERATOR
SPSCK
SS
VDD
SS
Figure 3. Full-duplex master-slave connections
Slave mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave MCU must be at `0'. SS must remain low until the transmission is complete. See Mode fault error on page 212. In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software must then read the SPI data register before another byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any particular SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
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A slave SPI must complete the write to the data register at least one bus cycle before the master SPI starts a transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. See Transmission formats on page 205. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
NOTE:
SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge.
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Serial Peripheral Interface Module (SPI) Transmission formats
Transmission formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate a multiple-master bus contention.
Clock phase and polarity controls
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
NOTE:
Before writing to the CPOL bit or the CPHA bit, the SPI should be disabled by clearing the SPI enable bit (SPE).
Transmission format when CPHA = O0O
Figure 4 shows an SPI transmission in which CPHA is `0'. The figure should not be used as a replacement for data sheet parametric information.Two waveforms are shown for SCK: one for CPOL = `0' and another for CPOL = `1'. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at `0', so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be
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high or must be reconfigured as general purpose I/O not affecting the SPI. See Mode fault error on page 212. When CPHA = `0', the first SPSCK edge is the MSB capture strobe. Therefore the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted.
SCK CYCLE # (FOR REFERENCE) SCK (CPOL ='0')
1
2
3
4
5
6
7
8
SCK (CPOL =1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 4. Transmission format (CPHA = `0')
MISO/MOSI MASTER SS SLAVE SS (CPHA ='0') SLAVE SS (CPHA = 1)
BYTE 1
BYTE 2
BYTE 3
Figure 5. CPHA/SS timing
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Serial Peripheral Interface Module (SPI) Transmission formats
Transmission format when CPHA = O1O
Figure 6 shows an SPI transmission in which CPHA is `1'. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = `0' and another for CPOL = `1'. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at `0', so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. See Mode fault error on page 212. When CPHA = `1', the master begins driving its MOSI pin on the first SPSCK edge. Therefore the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
1 2 3 4 5 6 7 8
SCK CYCLE # (FOR REFERENCE) SCK (CPOL ='0')
SCK (CPOL =1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 6. Transmission format (CPHA = `1')
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Transmission initiation latency When the SPI is configured as a master (SPMSTR = `1'), transmissions are started by a software write to the SPDR. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCK signal. When CPHA = `0', the SCK signal remains inactive for the first half of the first SCK cycle. When CPHA = `1', the first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. See Figure 7. The internal SPI clock in the master is a free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits are set to conserve power. SCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 7. This delay will be no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
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Serial Peripheral Interface Module (SPI) Transmission formats
WRITE TO SPDR BUS CLOCK MOSI SCK (CPHA = `1') SCK (CPHA ='0') SCK CYCLE NUMBER
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS CLOCK BUS CLOCK BUS CLOCK BUS CLOCK
WRITE TO SPDR
EARLIEST LATEST
WRITE TO SPDR
EARLIEST
WRITE TO SPDR
EARLIEST
WRITE TO SPDR
EARLIEST
Figure 7. Transmission start delay (master)
(SCK = INTERNAL CLOCK 2; 2 POSSIBLE START POINTS) (SCK = INTERNAL CLOCK 8; 8 POSSIBLE START POINTS) LATEST (SCK = INTERNAL CLOCK 32; 32 POSSIBLE START POINTS) LATEST (SCK = INTERNAL CLOCK 128; 128 POSSIBLE START POINTS) LATEST
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Error conditions
The following flags signal SPI error conditions: * Overflow (OVRF) -- failing to read the SPI data register before the next byte enters the shift register results in the OVRF bit becoming set. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. Mode fault error (MODF) -- the MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
*
Overflow error
The overflow flag (OVRF) becomes set if the SPI receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. See Figure 4 and Figure 6. If an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. Therefore, an overflow error always indicates the loss of data. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 10. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull the MCU out of wait mode instead. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 8 shows how it is possible to miss an overflow.
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Serial Peripheral Interface Module (SPI) Error conditions
BYTE 1 1
BYTE 2 4
BYTE 3 6
BYTE 4 8
SPRF
OVRF 2 5
READ SPSCR
READ SPDR 1 2 3 4
3 5 6 7 8
7 CPU READS SPSCRW WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS SET. BYTE 4 IS LOST.
BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT.
Figure 8. Missed read of overflow condition The first part of Figure 8 shows how to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF flag can be set in the interval between SPSCR and SPDR being read. In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. To prevent this, the OVRF interrupt should be enabled, or alternatively another read of the SPSCR should be carried out following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions will terminate with an SPRF interrupt. Figure 9 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
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BYTE 1 SPI RECEIVE COMPLETE SPRF 1
BYTE 2 5
BYTE 3 7
BYTE 4 11
OVRF 2 4 6 9 8 8 9 10 12 14
READ SPSCR
READ SPDR 1 2 3 4 5 6 7
3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
13
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 9. Clearing SPRF when OVRF interrupt is not enabled
Mode fault error
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 10. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS becomes `0'. A mode fault in a master SPI causes the following events to occur:
MC68HC08AZ32 212 Serial Peripheral Interface Module (SPI)
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MOTOROLA
Serial Peripheral Interface Module (SPI) Error conditions
* * * * *
If ERRIE = `1', the SPI generates an SPI receiver/error CPU interrupt request. The SPE bit is cleared. The SPTE bit is set. The SPI state counter is cleared. The data direction register of the shared I/O port regains control of port drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port. Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no function when SPE = `0'. Reading SPMSTR when MODF = `1' shows the difference between a MODF occurring when the SPI is a master and when it is a slave.
When configured as a slave (SPMSTR = `0'), the MODF flag is set if SS goes high during a transmission. When CPHA = `0', a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = `1', the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its IDLE level following the shift of the last data bit. See Transmission formats on page 205.
NOTE:
NOTE:
When CPHA = `0', a MODF occurs if a slave is selected (SS is at `0') and later deselected (SS is `1') even if no SPSCK is sent to that slave. This happens because SS at `0' indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = `0'. When CPHA = `1', a slave can be selected and then later deselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun.
In a slave SPI (MSTR = `0'), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by toggling the SPE bit of the slave.
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NOTE:
A `1' on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, the SPSCR should be read with the MODF bit set and then the SPCR register should be written to. This entire clearing mechanism must occur with no MODF condition existing or else the flag will not be cleared.
Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests: Table 3. SPI interrupts
Flag SPTE (Transmitter Empty) SPRF (Receiver Full) OVRF (Overflow) MODF (Mode Fault) Request SPI Transmitter CPU Interrupt Request (SPTIE = 1) SPI Receiver CPU Interrupt Request (SPRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = `1')
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests. The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF flag is enabled to generate receiver/error CPU interrupt requests.
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MOTOROLA
Serial Peripheral Interface Module (SPI) Queuing transmission data
SPTE
SPTIE
SPE SPI TRANSMITTER CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF
Figure 10. SPI interrupt request generation Two sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- the SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF can generate either an SPI receiver/error CPU interrupt request. SPI transmitter empty (SPTE) -- the SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate an SPTE CPU interrupt request.
*
Queuing transmission data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 11 shows the timing
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associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR
1
3
8
SPTE
2
5
10
PSCK (CPHA:CPOL =`1':0) MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 5 4 6 1
BYTE 1 SPRF 4
BYTE 2 9
BYTE 3
READ SPSCR
6
11
READ SPDR 1 2 3 4 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU READS SPSCR WITH SPRF BIT SET. 7 8 9
7 CPU READS SPDR, CLEARING SPRF BIT.
12
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT.
5 6
Figure 11. SPRF/SPTE CPU interrupt timing For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted.
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Serial Peripheral Interface Module (SPI) Resetting the SPI
Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: * * * * * The SPTE flag is set Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared, making it ready for a new complete transmission All the SPI port logic is defaulted back to being general purpose I/O.
The following items are reset only by a system reset: * * * All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing `0' to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
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Low-power modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
WAIT mode
The SPI module remains active after the execution of a WAIT instruction. In WAIT mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of WAIT mode. If SPI module functions are not required during WAIT mode, power consumption can be reduced by disabling the SPI module before executing the WAIT instruction. To exit WAIT mode when an overflow condition occurs, the OVRF bit should be enabled to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). See Interrupts on page 214.
STOP mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If STOP mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
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MOTOROLA
Serial Peripheral Interface Module (SPI) SPI during break interrupts
SPI during break interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear status bits during a break interrupt, a `1' should be written to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, a `0' should be written to the BCFE bit. With BCFE at `0' (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is a `0'. After the break, the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register in break mode will not initiate a transmission, nor will this data be transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
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I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. * * * * * MISO -- data received MOSI -- data transmitted SPSCK -- serial clock SS -- slave select VSS -- clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD.
MISO (Master in/Slave out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is `0' and its SS pin is at `0'. To support a multiple-slave system, a `1' on the SS pin puts the MISO pin in a high-impedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port.
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Serial Peripheral Interface Module (SPI) I/O Signals
MOSI (Master out/Slave in)
MOSI is one of the two SPI module pins that transmits serial data. In full duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port.
SPSCK (serial clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port.
SS (slave select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = `0', the SS is used to define the start of a transmission. See Transmission formats on page 205. Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = `0' format. However, it can remain low throughout the transmission for the CPHA = `1' format. See Figure 12.
MISO/MOSI MASTER SS SLAVE SS (CPHA ='0') SLAVE SS (CPHA = `1')
BYTE 1
BYTE 2
BYTE 3
Figure 12. CPHA/SS timing
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When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. See SPI status and control register (SPSCR) on page 226.
NOTE:
A `1' on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if transmission has already begun.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. See Mode fault error on page 212. For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the data register. See Table 4. Table 4. SPI configuration
SPE 0 1 1 1 SPMSTR MODFEN SPI CONFIGURATION X(1) 0 1 1 X X 0 1 Not Enabled Slave Master without MODF Master with MODF STATE OF SS LOGIC General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI
1. X = don't care
VSS (clock ground)
VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, the ground pin should be connected of the slave to the VSS pin.
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MOTOROLA
Serial Peripheral Interface Module (SPI) I/O registers
I/O registers
Three registers control and monitor SPI operation: * * * SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR)
SPI control register (SPCR)
The SPI control register does the following: * * * * * * Enables SPI module interrupt requests Selects CPU interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module
6 5 4 3 2 1 Bit 0
Bit 7 SPCR Read:
SPRIE
Write: Reset: 0 R
R
0
SPMSTR
1
CPOL
0
CPHA
1
SPWOM
0
SPE
0
SPTIE
0
= Reserved
Figure 13. SPI control register (SPCR) SPRIE -- SPI receiver interrupt enable This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled
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SPMSTR -- SPI master This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock polarity This read/write bit determines the logic state of the SPSCK pin between transmissions. See Figure 4 and Figure 6. To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit. CPHA -- Clock phase This read/write bit controls the timing relationship between the serial clock and SPI data. See Figure 4 and Figure 6. To transmit data between SPI modules, the SPI modules must have identical CPHA bits. When CPHA = `0', the SS pin of the slave SPI module must be set to logic one between bytes. See Figure 12. Reset sets the CPHA bit. When CPHA ='0' for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. When CPHA = `1' for a slave, the first edge of the SPSCK indicates the beginning of the transmission. The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. See Mode fault error on page 212. A `1' on the SS pin does not affect the state of the SPI state machine in any way. SPWOM -- SPI wired-OR mode This read/write bit disables the pull-up devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins
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MOTOROLA
Serial Peripheral Interface Module (SPI) I/O registers
0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See Resetting the SPI on page 217. Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI transmit interrupt enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled
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SPI status and control register (SPSCR) The SPI status and control register contains flags to signal the following conditions: * * * * Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty
The SPI status and control register also contains bits that perform the following functions: * * * Enable error interrupts Enable mode fault error detection Select master SPI baud rate
Bit 7 SPSCR Read: Write: Reset: 6 5 4 3 2 1 Bit 0
SPRF ERRIE R
0 R 0 = Reserved
OVRF R
0
MODF R
0
SPTE R
1
MODFE N
0
SPR1
0
SPR0
0
Figure 14. SPI status and control register (SPSCR) SPRF -- SPI receiver full This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the SPRF bit. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full
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MOTOROLA
Serial Peripheral Interface Module (SPI) I/O registers
ERRIE -- Error interrupt enable This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow flag This clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the SPI data register. Reset clears the OVRF flag. 1 = Overflow 0 = No overflow MODF -- Mode fault This clearable, ready-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading the SPI status and control register with MODF set and then writing to the SPI data register. Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI transmitter empty This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also.
NOTE:
The SPI data register should not be written to unless the SPTE bit is high.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is
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completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN -- Mode fault enable This read/write bit, when set to `1', allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general purpose I/O. If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general purpose I/O regardless of the value of MODFEN. See SS (slave select) on page 221. If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See Mode fault error on page 212. SPR1 and SPR0 -- SPI baud rate select In master mode, these read/write bits select one of four baud rates as shown in Table 5. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 5. SPI master baud rate selection
SPR1:SPR0 00 01 10 11 Baud rate divisor (BD) 2 8 32 128
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MOTOROLA
Serial Peripheral Interface Module (SPI) I/O registers
The following formula is used to calculate the SPI baud rate: CGMOUT Baud rate = --------------------------2 x BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor
SPI data register (SPDR)
The SPI data register is the read/write buffer for the receive data register and the transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate buffers that can contain different values. See Figure 2.
Bit 7 6 5 4 3 2 1 Bit 0
SPDR
Read: Write: Reset:
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
Indeterminate after reset
Figure 15. SPI data register (SPDR) R7:R0/T7:T0 -- Receive/Transmit data bits
NOTE:
Read-modify-write instructions should not be used on the SPI data register since the buffer read is not the same as the buffer written.
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Serial Peripheral Interface Module (SPI)
MC68HC08AZ32 230 Serial Peripheral Interface Module (SPI)
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MOTOROLA
Timer Interface Module A (TIMA) TIMA
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 TIMA counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Pulse width modulation (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Unbuffered PWM signal generation . . . . . . . . . . . . . . . . . . . . . 239 Buffered PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . 240 PWM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 TIMA during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 TIMA clock pin (PTD6/TACLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 TIMA channel I/O pins (PTF1/TACH3-PTE2/TACH0) . . . . . . . . . 245 I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TIMA status and control register (TASC) . . . . . . . . . . . . . . . . . . . 246 TIMA counter registers (TACNTH:TACNTL). . . . . . . . . . . . . . . . . 248 TIMA counter modulo registers (TAMODH/L). . . . . . . . . . . . . . . . 249 TIMA channel status and control registers (TASC0-TASC3) . . . . 250 TIMA channel registers (TACH0H/L-TACHH/L). . . . . . . . . . . . . . 254
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Timer Interface Module A (TIMA)
Introduction
This section describes the timer interface module (TIMA). The TIMA is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 1 is a block diagram of the TIMA.
Features
Features of the TIMA include the following: * Four input capture/output compare channels - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * * Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIMA clock input - Seven-frequency internal bus clock prescaler selection - External TIMA clock input (4MHz maximum frequency) * * * * Free-running or modulo up-count operation Toggle any channel pin on overflow TIMA counter stop and reset bits Modular architecture expandable to 8 channels
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Timer Interface Module A (TIMA) Functional description
Functional description
Figure 1 shows the structure of the TIMA. The central component of the TIMA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing reference for the input capture and output compare functions. The TIMA counter modulo registers, TAMODH:TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The four TIMA channels are programmable independently as input capture or output compare channels.
TIMA counter prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
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PTD6/TACLK INTERNAL BUS CLOCK TSTOP TRST
TACLK PRESCALER SELECT PRESCALER
PS2
PS1
PS0
16-BIT COUNTER 16-BIT COMPARATOR TAMODH:TAMODL
TOF TOIE
INTERRUPT LOGIC
TOV0 CHANNEL 0 16-BIT COMPARATOR TACH0H:TACH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TACH1H:TACH1L 16-BIT LATCH MS1A CH1IE TOV2 CHANNEL 2 16-BIT COMPARATOR TACH2H:TACH2L 16-BIT LATCH MS2A MS2B TOV3 CHANNEL 3 16-BIT COMPARATOR TACH3H:TACH3L 16-BIT LATCH MS3A CH3IE CH3F INTERRUPT LOGIC ELS3B ELS3A CH3MAX PTF1 LOGIC PTF1/TACH CH2IE CH2F INTERRUPT LOGIC ELS2B ELS2A CH2MAX PTF0 LOGIC PTF0/TACH CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PTE3 LOGIC PTE3/TACH CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PTE2 LOGIC PTE2/TACH
Figure 1. TIMA block diagram
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Timer Interface Module A (TIMA) Functional description
Table 1. TIMA I/O register summary
Register Name Bit 7 6 5 4 3 0 11 3 11 3 2 PS2 10 2 10 2 1 PS1 9 1 9 1 Bit 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 Addr. $0020 $0022 $0023 $0024 $0025
TIMA status/control register (TASC) TOF TIMA counter register high (TACNTH) Bit 15 TIMA counter register low (TACNTL) Bit 7 TIMA Counter modulo reg. high (TAMODH) Bit 15 TIMA counter modulo reg. low (TAMODL) Bit 7
TOIE TSTOP TRST 14 6 14 6 13 5 13 5 12 4 12 4
TIMA Ch. 0 Status/control register (TASC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX$0026 TIMA Ch. 0 register high (TACH0H) Bit 15 TIMA Ch. 0 register low (TACH0L) Bit 7 14 6 13 5 12 4 11 3 10 2 9 1 Bit 8 Bit 0 $0027 $0028
TIMA Ch. 1 status/control register (TASC1) CH1F CH1IE TIMA Ch. 1 register high (TACH1H) Bit 15 TIMA Ch. 1 register Low (TACH1L) Bit 7 14 6 13 5
MS1A ELS1B ELS1A TOV1 CH1MAX$0029 12 4 11 3 10 2 9 1 Bit 8 Bit 0 $002A $002B
TIMA Ch. 2 Status/Control register (TASC2) CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX$002C TIMA Ch. 2 register High (TACH2H) Bit 15 TIMA Ch. 2 register Low (TACH2L) Bit 7 14 6 13 5 12 4 11 3 10 2 9 1 Bit 8 Bit 0 $002D $002E
TIMA Ch. 3 Status/Control register (TASC3) CH3F CH3IE TIMA Ch. 3 register High (TACH3H) Bit 15 TIMA Ch. 3 register Low (TACH3L) Bit 7 14 6 13 5
MS3A ELS3B ELS3A TOV3 CH3MAX$002F 12 4 11 3 10 2 9 1 Bit 8 Bit 0 $0030 $0031
= Unimplemented
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Timer Interface Module A (TIMA)
Input capture With the input capture function, the TIMA can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH:TACHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
Output compare
With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. Any output compare channel can generate unbuffered output compare pulses as described in Output compare on page 236. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.
Unbuffered output compare
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Timer Interface Module A (TIMA) Functional description
*
When changing to a larger output compare value, enable channel x TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
Buffered output compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors the buffered output compare function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The output compare value in the TIMA channel 2 registers initially controls the output on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
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Timer Interface Module A (TIMA)
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares.
Pulse width modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 2 shows, the output compare value in the TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIMA to set the pin if the state of the PWM pulse is logic zero.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE WIDTH PTE/F/x/TACHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 2. PWM period and pulse width The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select
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Timer Interface Module A (TIMA) Functional description
value is $000. See TIMA status and control register (TASC) on page 246. The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50%. Unbuffered PWM signal generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse width modulation (PWM) on page 238. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMA may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable channel x TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
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Timer Interface Module A (TIMA)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
Buffered PWM signal generation
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Timer Interface Module A (TIMA) Functional description
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMA status and control register (TASC): a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH:TAMODL), write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH:TACHxL), write the value for the required pulse width. 4. In TIMA channel x status and control register (TASCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 3. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 3.
PWM initialization
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
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Timer Interface Module A (TIMA)
5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H:TACH0L) initially control the buffered PWM output. TIMA status control register 0 (TASCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H:TACH2L) initially control the PWM output. TIMA status control register 2 (TASCR2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100% duty cycle output. See TIMA channel status and control registers (TASC0-TASC3) on page 250.
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Timer Interface Module A (TIMA) Interrupts
Interrupts
The following TIMA sources can generate interrupt requests: * TIMA overflow flag (TOF) -- The TOF bit is set when the TIMA counter value rolls over to $0000 after matching the value in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE, enables TIMA overflow CPU interrupt requests. TOF and TOIE are in the TIMA status and control register. TIMA channel flags (CH3F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE= 1. CHxF and CHxIE are in the TIMA channel x status and control register.
*
*
Low-power modes
The WAIT instruction puts the MCU in low-power-consumption standby mode.
Wait mode
The TIMA remains active after the execution of a WAIT instruction. In wait mode the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction.
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Timer Interface Module A (TIMA)
TIMA during break interrupts
A break interrupt stops the TIMA counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.
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Timer Interface Module A (TIMA) I/O Signals
I/O Signals
Ports E and F each share two pins with the TIM and Port D shares one. PTD6/TACLK is an external clock input to the TIMA prescaler. The four TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, and PTF1/TACH3.
TIMA clock pin (PTD6/TACLK)
PTD6/TACLK is an external clock input that can be the clock source for the TIMA counter instead of the prescaled internal bus clock. Select the PTD6/TACLK input by writing logic ones to the three prescaler select bits, PS[2:0]. See TIMA status and control register (TASC) on page 246. The minimum TACLK pulse width, TACLKLMIN or TACLKHMIN, is: 1 --------------------------------- + t SU bus frequency The maximum TCLK frequency is: bus frequency / 2 PTD6/TACLK is available as a general-purpose I/O pin when not used as the TIMA clock input. When the PTD6/TACLK pin is the TIMA clock input, it is an input regardless of the state of the DDRD6 bit in data direction register D.
TIMA channel I/O pins (PTF1/TACH3PTE2 /TACH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF0/TACH2 and PTE3/TACH1 can be configured as buffered output compare or buffered PWM pins.
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Timer Interface Module A (TIMA)
I/O registers
The following I/O registers control and monitor operation of the TIMA: * * * * * TIMA status and control register (TASC) TIMA control registers (TACNTH:TACNTL) TIMA counter modulo registers (TAMODH:TAMODL) TIMA channel status and control registers (TASC0, TASC1, TASC2, and TASC3) TIMA channel registers (TACH0H:TACH0L, TACH1H:TACH1L, TACH2H:TACH2L, and TACH3H:TACH3L)
TIMA status and control register (TASC)
The TIMA status and control register does the following: * * * * * Enables TIMA overflow interrupts Flags TIMA overflows Stops the TIMA counter Resets the TIMA counter Prescales the TIMA counter clock
Bit 7 6 5 4 3 2 1 Bit 0
TASC $0020
Read: Write: Reset:
TOF TOIE 0
0 0 1
0 TSTOP TRST
0
0 PS2
0 0
PS1
0
PS0
0
= Unimplemented
Figure 3. TIMA status and control register (TASC)
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Timer Interface Module A (TIMA) I/O registers
TOF -- TIMA Overflow Flag Bit This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic zero to TOF. If another TIMA overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic one to TOF has no effect. 1 = TIMA counter has reached modulo value 0 = TIMA counter has not reached modulo value TOIE -- TIMA Overflow Interrupt Enable Bit This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled TSTOP -- TIMA Stop Bit This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit. 1 = TIMA counter stopped 0 = TIMA counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit wait mode.
TRST -- TIMA Reset Bit Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA counter is reset and always reads as logic zero. Reset clears the TRST bit. 1 = Prescaler and TIMA counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000.
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Timer Interface Module A (TIMA)
PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTD6/TACLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 2 shows. Reset clears the PS[2:0] bits. Table 2. Prescaler selection
PS[2:0] 000 001 010 011 100 101 110 111 TIMA clock source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD6/TACLK
TIMA counter registers (TACNTH:TACNTL)
The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter. Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers
NOTE:
If you read TACNTH during a break interrupt, be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value latched during the break.
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Timer Interface Module A (TIMA) I/O registers
Bit 7 TACNTH $0022 Read: Write: Reset: 0 Bit 7 TACNTL $0023 Read: Write: 0 Reset:
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
= Unimplemented
Figure 4. TIMA counter registers (TACNTH:TACNTL)
TIMA counter modulo registers (TAMODH/L)
The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes counting from $0000 at the next clock. Writing to the high byte (TAMODH) inhibits the TOF bit and overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo registers.
Bit 7 6 5 4 3 2 1 Bit 0
TAMODH $0024
Read:
Bit 15
Write: Reset: 1
14
1
13
1
12
1
11
1
10
1
9
1
Bit 8
1
Bit 7
TAMODL $0025 Read:
6 6
1
5 5
1
4 4
1
3 3
1
2 2
1
1 1
1
Bit 0 Bit 0
1
Bit 7
Write: Reset: 1
Figure 5. TIMA counter modulo registers (TAMODH:TAMODL)
NOTE:
Reset the TIMA counter before writing to the TIMA counter modulo registers.
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MC68HC08AZ32 Timer Interface Module A (TIMA) 249
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Timer Interface Module A (TIMA)
TIMA channel status and control registers (TASC0TASC3) Each of the TIMA channel status and control registers does the following: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIMA overflow Selects 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Bit 7 TASC0 $0026 Read: Write: Reset: 6 5 4 3 2 1 Bit 0
CH0F CH0IE 0
0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
TASC1 $0029
Read: Write: Reset:
CH1F CH1IE 0
0 Bit 7 0 6
0 MS1A
0 5 0 4
ELS1B
0 3
ELS1A
0 2
TOV1
0 1
CH1MAX
0 Bit 0
TASC2 $002C
Read: Write: Reset:
CH2F CH2IE 0
0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
TASC3 $002F
Read: Write: Reset:
CH3F CH3IE 0
0 0
0 MS3A
0 0
ELS3B
0
ELS3A
0
TOV3
0
CH3MAX
0
= Unimplemented
Figure 6. TIMA channel status and control registers (TASC0-TASC3)
MC68HC08AZ32 250 Timer Interface Module A (TIMA)
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Timer Interface Module A (TIMA) I/O registers
CHxF-- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMA counter registers matches the value in the TIMA channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIMA channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0 and TIMA channel 2 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1B to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TCH3B to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled
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MC68HC08AZ32 Timer Interface Module A (TIMA) 251
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Timer Interface Module A (TIMA)
MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TBCHx pin. See Table 3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TASC).
ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E, and pin PTEx/TBCHx is available as a general-purpose I/O pin. Table 3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
MC68HC08AZ32 252 Timer Interface Module A (TIMA)
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Timer Interface Module A (TIMA) I/O registers
Table 3. Mode, edge, and level selection
MSxB:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X ELSxB:ELSxA 00 Output Preset 00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare mode configuration Pin under Port Control; Initial Output Level High
NOTE:
Before enabling a TIMA channel register for input capture operation, make sure that the PTE/TCHxB pin is stable for at least two bus clocks.
TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMA counter overflow. 0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE:
When TOVx is set, a TIMA counter overflow takes precedence over a channel x output compare if both occur at the same time.
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MC68HC08AZ32 Timer Interface Module A (TIMA) 253
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Timer Interface Module A (TIMA)
CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic zero, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 7 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
PTE/F/x/TACHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 7. CHxMAX Latency
TIMA channel registers (TACH0H/LTACHH /L)
These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIMA channel x registers (TACHxH) inhibits input captures until the low byte (TACHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIMA channel x registers (TACHxH) inhibits output compares until the low byte (TACHxL) is written.
Bit 7 6 5 4 3 2 1 Bit 0
TACH0H $0027
Read:
Bit 15
Write: Reset:
14
13
12
11
10
9
Bit 8
Indeterminate after reset
Figure 8. TIMA channel registers (TACH0H/L-TACH3H/L)
MC68HC08AZ32 254 Timer Interface Module A (TIMA)
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Timer Interface Module A (TIMA) I/O registers
Bit 7 TACH0L $0028 Read:
6
5
4
3
2
1
Bit 0
Bit 7
Write: Reset: Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TACH1H $002A
Read:
Bit 15
Write: Reset: Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TACH1L $002B
Read:
Bit 7
Write: Reset: Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TACH2H $002D
Read:
Bit 15
Write: Reset: Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TACH2L $002E
Read:
Bit 7
Write: Reset: Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TACH3H $0030
Reset:
Bit 15
Write:
14
13
12
11
10
9
Bit 8
Reset:
Bit 7 TACH3L $0031 Read: 6 5
Indeterminate after reset 4 3 2 1 Bit 0
Bit 7
Write: Reset:
6
5
4
3
2
1
Bit 0
Indeterminate after reset
Figure 8. TIMA channel registers (TACH0H/L-TACH3H/L) (Continued)
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MC68HC08AZ32 Timer Interface Module A (TIMA) 255
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Timer Interface Module A (TIMA)
MC68HC08AZ32 256 Timer Interface Module A (TIMA)
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Timer Interface Module B (TIMB) TIMB
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 TIMB counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Unbuffered PWM signal generation . . . . . . . . . . . . . . . . . . . . . 264 Buffered PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . 265 PWM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 TIMB during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 TIMB clock Pin (PTD4/TBLCK). . . . . . . . . . . . . . . . . . . . . . . . . . . 269 TIMB channel I/O pins (PTF5/TBCH1-PTF4/TBCH0) . . . . . . . . . 269 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 TIMB status and control register (TBSC) . . . . . . . . . . . . . . . . . . . 270 TIMB counter registers (TBCNTH:TBCNTL). . . . . . . . . . . . . . . . . 272 TIMB counter modulo registers (TBMODH:TBMOD) . . . . . . . . . . 273 TIMB channel status and control registers (TBSC0-TBSC1) . . . . 274 TIMB channel registers (TBCH0H/ L-TBCH3H/L) . . . . . . . . . . . . 278
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MC68HC08AZ32 Timer Interface Module B (TIMB) 257
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Timer Interface Module B (TIMB)
Introduction
This section describes the timer interface module (TIMB). The TIMB is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 9 is a block diagram of the TIMB.
Features
Features of the TIMB include the following: * Two Input capture/output compare channels - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * * Buffered and unbuffered Pulse Width Modulation (PWM) signal generation Programmable TIMB clock input - Seven-frequency internal bus clock prescaler selection - External TIMB Clock Input (4-MHz Maximum Frequency) * * * * Free-running or modulo up-count operation Toggle any channel pin on overflow TIMB counter stop and reset bits Modular architecture expandable to 8 channels
MC68HC08AZ32 258 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) Functional description
Functional description
Figure 9 shows the structure of the TIMB. The central component of the TIMB is the 16-bit TIMB counter that can operate as a free-running counter or a modulo up-counter. The TIMB counter provides the timing reference for the input capture and output compare functions. The TIMB counter modulo registers, TBMODH:TBMODL, control the modulo value of the TIMB counter. Software can read the TIMB counter value at any time without affecting the counting sequence. The two TIMB channels are programmable independently as input capture or output compare channels.
TIMB counter prescaler
The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin, PTD4/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source.
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MC68HC08AZ32 Timer Interface Module B (TIMB) 259
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Timer Interface Module B (TIMB)
PTD4/TBCLK INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER
TBCLK PRESCALER SELECT PRESCALER
PS2
PS1
PS0 CANTIMCAP TOF TOIE INTERRUPT LOGIC CANTIMCAP TOV0
16-BIT COMPARATOR TBMODH:TBMODL
CHANNEL 0 16-BIT COMPARATOR TBCH0H:TBCH0L 16-BIT LATCH
ELS0B
ELS0A
CH0MAX
PTF2 LOGIC
PTF4/TBCH
CH0F INTERRUPT LOGIC
MS0A MS0B
CH0IE TOV1
INTERNAL BUS
CHANNEL 1 16-BIT COMPARATOR TBCH1H:TBCH1L 16-BIT LATCH
ELS1B
ELS1A
CH1MAX
PTF3 LOGIC
PTF5/TBCH
CH1F INTERRUPT LOGIC
MS1A
CH1IE
Figure 9. TIMB block diagram
MC68HC08AZ32 260 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) Functional description
Input capture
With the input capture function, the TIMB can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers, TBCHxH:TBCHxL. The polarity of the active edge is programmable. Input captures can generate TIMB CPU interrupt requests.
Output compare
With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMB can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. Any output compare channel can generate unbuffered output compare pulses as described in Output compare on page 261. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMB overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMB may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.
Unbuffered output compare
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MC68HC08AZ32 Timer Interface Module B (TIMB) 261
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Timer Interface Module B (TIMB)
* When changing to a larger output compare value, enable channel x TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
Buffered output compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the output are the ones written to last. TBSC0 controls and monitors the buffered output compare function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares.
Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time between overflows is the period of the PWM signal.
MC68HC08AZ32 262 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) Functional description
As Figure 10 shows, the output compare value in the TIMB channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIMB to set the pin if the state of the PWM pulse is logic zero.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE WIDTH PTFx/TBCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10. PWM period and pulse width The value in the TIMB counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See TIMB status and control register (TBSC) on page 270. The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers produces a duty cycle of 128/256 or 50%.
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MC68HC08AZ32 Timer Interface Module B (TIMB) 263
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Timer Interface Module B (TIMB)
Unbuffered PWM signal generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 262. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMB may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable channel x TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
MC68HC08AZ32 264 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) Functional description
Buffered PWM signal generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b. Reset the TIMB counter by setting the TIMB reset bit, TRST. 2. In the TIMB counter modulo registers (TBMODH:TBMODL), write the value for the required PWM period. 3. In the TIMB channel x registers (TBCHxH:TBCHxL), write the value for the required pulse width. 4. In TIMB channel x status and control register (TBSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 1 b. Write 1 to the toggle-on-overflow bit, TOVx.
PWM initialization
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MC68HC08AZ32 Timer Interface Module B (TIMB) 265
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Timer Interface Module B (TIMB)
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 1)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC), clear the TIMB stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMB channel 0 registers (TBCH0H:TBCH0L) initially control the buffered PWM output. TIMB status control register 0 (TBSCR0) controls and monitors the PWM signal from the linked channels. MS0B Takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100% duty cycle output. See TIMB channel status and control registers (TBSC0-TBSC1) on page 274.
MC68HC08AZ32 266 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) Interrupts
Interrupts
The following TIMB sources can generate interrupt requests: * TIMB overflow flag (TOF) -- The TOF bit is set when the TIMB counter value rolls over to $0000 after matching the value in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit, TOIE, enables TIMB overflow CPU interrupt requests. TOF and TOIE are in the TIMB status and control register. TIMB channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIMB channel x status and control register.
*
Low-power modes
The WAIT instruction puts the MCU in low-power-consumption standby mode.
WAIT mode
The TIMB remains active after the execution of a WAIT instruction. In wait mode the TIMB registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of wait mode. If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB before executing the WAIT instruction.
11-timb
MC68HC08AZ32 Timer Interface Module B (TIMB) 267
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Timer Interface Module B (TIMB)
TIMB during break interrupts
A break interrupt stops the TIMB counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.
MC68HC08AZ32 268 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) I/O Signals
I/O Signals
Port F Shares two of its pins with the TIMB and Port D shares one. PTD4/TBCLK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and PTF5/TBCH1.
TIMB clock Pin (PTD4/TBLCK)
PTD4/TBCLK is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock. Select the PTD4/TBCLK input by writing logic ones to the three prescaler select bits, PS[2:0]. See TIMB status and control register (TBSC) on page 270. The minimum TBCLK pulse width, TBCLKLMIN or TBCLKHMIN, is: 1 --------------------------------- + t SU bus frequency The maximum TCLK frequency is: bus frequency / 2 is available as a general-purpose I/O pin when not used as the TIMB clock input. When the PTD4/TBCLK pin is the TIMB clock input, it is an input regardless of the state of the DDR5 bit in data direction register D.
TIMB channel I/O pins (PTF5/TBCH1PTF4/ TBCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF5/TBCH1 and PTF4/TBCH0 can be configured as buffered output compare or buffered PWM pins. TBCH0 has an additional source for the input capture signal i.e CANTIMCAP. See Figure 9 This signal is generated by the msCAN08 which generates a timer signal whenever a valid frame has been received or transmitted. The signal is routed into TBCH0 under the control of the Timer Link Enable (TLNKEN) bit in the CMCR0 see 23.12.2 msCAN08 module control register (CMCR0).
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MC68HC08AZ32 Timer Interface Module B (TIMB) 269
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Timer Interface Module B (TIMB)
I/O Registers
The following I/O registers control and monitor operation of the TIM: * * * * * TIMB status and control register (TBSC) TIMB control registers (TBCNTH:TBCNTL) TIMB counter modulo registers (TBMODH:TBMODL) TIMB channel status and control registers (TBSC0 and TBSC1) TIMB channel registers (TBCH0H:TBCH0L and TBCH1H:TBCH1L)
TIMB status and control register (TBSC)
The TIMB status and control register does the following: * * * * * Enables TIMB overflow interrupts Flags TIMB overflows Stops the TIMB counter Resets the TIMB counter Prescales the TIMB counter clock
MC68HC08AZ32 270 Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB) I/O Registers
Bit 7 TBSC $0040 Read: Write: Reset:
6
5
4
3
2
1
Bit 0
TOF TOIE 0
0 0 1
0 TSTOP TRST
0
0 PS2
0 0
PS1
0
PS0
0
= Unimplemented
Figure 11. TIMB status and control register (TBSC) TOF -- TIMB overflow flag bit This read/write flag is set when the TIMB counter resets to $0000 after reaching the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic zero to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic one to TOF has no effect. 1 = TIMB counter has reached modulo value 0 = TIMB counter has not reached modulo value TOIE -- TIMB overflow interrupt enable bit This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMB overflow interrupts enabled 0 = TIMB overflow interrupts disabled TSTOP -- TIMB stop bit This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit. 1 = TIMB counter stopped 0 = TIMB counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMB is required to exit wait mode.
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MC68HC08AZ32 Timer Interface Module B (TIMB) 271
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Timer Interface Module B (TIMB)
TRST -- TIMB reset bit Setting this write-only bit resets the TIMB counter and the TIMB prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMB counter is reset and always reads as logic zero. Reset clears the TRST bit. 1 = Prescaler and TIMB counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIMB counter at a value of $0000.
PS[2:0] -- Prescaler select bits These read/write bits select either the PTD5 pin or one of the seven prescaler outputs as the input to the TIMB counter as Table 1 shows. Reset clears the PS[2:0] bits. Table 1. Prescaler selection
PS[2:0] 000 001 010 011 100 101 110 111 TIMB Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD4/TBLCK
TIMB counter registers (TBCNTH:TBCNTL)
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
MC68HC08AZ32 272 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) I/O Registers
NOTE:
If you read TBCNTH during a break interrupt, be sure to unlatch TBCNTL by reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL retains the value latched during the break.
Bit 7 6 5 4 3 2 1 Bit 0
TBCNTH $0041
Read: Write: Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
TBCNTL $0042
Read: Write:
Bit 7
6
5
4
3
2
1
Bit 0
0 Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 12. TIMB counter registers (TBCNTH:TBCNTL)
TIMB counter modulo registers (TBMODH:TBMOD)
The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMB counter resumes counting from $0000 at the next clock. Writing to the high byte (TBMODH) inhibits the TOF bit and overflow interrupts until the low byte (TBMODL) is written. Reset sets the TIMB counter modulo registers.
Bit 7 6 5 4 3 2 1 Bit 0
TBMODH $0043
Read:
Bit 15
Write: Reset: 1
14
1
13
1
12
1
11
1
10
1
9
1
Bit 8
1
Bit 7
TBMODL $0044 Read:
6 6
1
5 5
1
4 4
1
3 3
1
2 2
1
1 1
1
Bit 0 Bit 0
1
Bit 7
Write: Reset: 1
Figure 13. TIMB counter modulo registers (TBMODH:TBMODL)
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MC68HC08AZ32 Timer Interface Module B (TIMB) 273
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Timer Interface Module B (TIMB)
NOTE:
Reset the TIMB counter before writing to the TIMB counter modulo registers.
TIMB channel status and control registers (TBSC0TBSC1)
Each of the TIMB channel status and control registers does the following: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIMB overflow Selects 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Bit 7 6 5 4 3 2 1 Bit 0
TBSC0 $0045
Read: Write: Reset:
CH0F CH0IE 0
0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
TBSC1 $0048
Read: Write: Reset: Reset:
CH1F CH1IE 0
0 0 0 0
0 MS1A
0 0 0 0
ELS1B
0 0
ELS1A
0 0
TOV1
0 0
CH1MAX
0 0
= Unimplemented
Figure 14. TIMB channel status and control registers (TBSC0-TBSC1)
MC68HC08AZ32 274 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) I/O Registers
CHxF-- Channel x flag bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMB counter registers matches the value in the TIMB channel x registers. When TIMB CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading TIMB channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x interrupt enable bit This read/write bit enables TIMB CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode select bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. 1 = Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode select bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 1. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation
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MC68HC08AZ32 Timer Interface Module B (TIMB) 275
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Timer Interface Module B (TIMB)
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 1. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMB status and control register (TSC).
ELSxB and ELSxA -- Edge/level select bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port F, and pin PTFx/TBCHx is available as a general-purpose I/O pin. Table 1 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 1. Mode, edge, and level selection
MSxB:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X
ELSxB:ELSxA 00
Mode Output Preset
Configuration Pin under Port Control; Initial Output Level High Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only
00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture
Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare
MC68HC08AZ32 276 Timer Interface Module B (TIMB)
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MOTOROLA
Timer Interface Module B (TIMB) I/O Registers
NOTE:
Before enabling a TIMB channel register for input capture operation, make sure that the PTFx/TBCHx pin is stable for at least two bus clocks.
TOVx -- Toggle-on-overflow bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMB counter overflow. 0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE:
When TOVx is set, a TIMB counter overflow Takes precedence over a channel x output compare if both occur at the same time.
CHxMAX -- Channel x maximum duty cycle bit When the TOVx bit is at logic zero, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 15 shows, the CHxMAX bit Takes effect in the cycle after it is set or cleared. The output stabs at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTFx/TBCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 15. CHxMAX latency
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MC68HC08AZ32 Timer Interface Module B (TIMB) 277
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Timer Interface Module B (TIMB)
TIMB channel registers (TBCH0H/ LTBCH3H/L) These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIMB channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIMB channel x registers (TBCHxH) inhibits output compares until the low byte (TBCHxL) is written.
Bit 7 TBCH0H $0046 Read: 6 5 4 3 2 1 Bit 0
Bit 15
Write: Reset: Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TBCH0L $0047
Read:
Bit 7
Write: Reset: Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TBCH1H $0049
Read:
Bit 15
Write: Reset: Bit 7
14
13
12
11
10
9
Bit 8
Indeterminate after reset 6 5 4 3 2 1 Bit 0
TBCH1L $004A
Read:
Bit 7
Write: Reset:
6
5
4
3
2
1
Bit 0
Indeterminate after reset
Figure 16. TIMB channel registers (TBCH0H/L-TBCH1H/L)
MC68HC08AZ32 278 Timer Interface Module B (TIMB)
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MOTOROLA
Programmable Interrupt Timer (PIT) PIT
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 PIT counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 PIT during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 PIT status and control register (PSC) . . . . . . . . . . . . . . . . . . . . . . 283 PIT counter registers (PCNTH:PCNTL) . . . . . . . . . . . . . . . . . . . . 285 PIT Counter modulo registers (PMODH:PMODL) . . . . . . . . . . . . 286
Introduction
This section describes the periodic interrupt timer module (PIT). Figure 1 is a block diagram of the PIT.
Features
Features of the PIT include the following: * * * Programmable PIT Clock Input Free-Running or Modulo Up-Count Operation PIT Counter Stop and Reset Bits
1-pit
MC68HC08AZ32 Programmable Interrupt Timer (PIT) 279
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Programmable Interrupt Timer (PIT)
Functional Description
Figure 1 shows the structure of the PIT. The central component of the PIT is the 16-bit PIT counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers, PMODH:PMODL, control the modulo value of the counter. Software can read the counter value at any time without affecting the counting sequence.
INTERNAL BUS CLOCK CSTOP CRST
PRESCALER SELECT PRESCALER
PPS2
PPS1
PPS0
16-BIT COUNTER 16-BIT COMPARATOR PITTMODH:PITTMODL
POF PIE
INTERRUPT LOGIC
Figure 1. PIT Block Diagram Table 1. PIT I/O Register Summary
Register Name Bit 7 6 PIE 14 6 14 6 5 4 3 0 11 3 11 3 2 1 Bit 0 Addr.
PIT Status/Control Register (PSC) POF PIT Counter Register. High (PCNTH) Bit 15 PIT Counter Register. Low (PCNTL) 7
PSTOP PRST 13 5 13 5 12 4 12 4
PPS2 PPS1 PPS0 $004B 10 2 10 2 9 1 9 1 8 0 $004C $004D
PIT Counter Modulo Reg. High (PMODH) Bit 15 PIT Counter Modulo Reg. Low (PMODL) Bit 7
Bit 8 $004E Bit 0 $004F
MC68HC08AZ32 280 Programmable Interrupt Timer (PIT)
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MOTOROLA
Programmable Interrupt Timer (PIT) Low-power modes
PIT counter prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PPS[2:0] in the status and control register select the PIT clock source. The value in the PIT counter modulo registers and the selected prescaler output determines the frequency of the Periodic Interrupt. The PIT overflow flag (POF) is set when the PIT counter value rolls over to $0000 after matching the value in the PIT counter modulo registers. The PIT interrupt enable bit, PIE, enables PIT overflow CPU interrupt requests. POF and PIE are in the PIT status and control register.
Low-power modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
WAIT mode
The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait mode. If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before executing the WAIT instruction.
STOP mode
The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode after an external interrupt.
3-pit
MC68HC08AZ32 Programmable Interrupt Timer (PIT) 281
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Programmable Interrupt Timer (PIT)
PIT during break interrupts
A break interrupt stops the PIT counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM break flag control register (SBFCR) on page 90. To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.
MC68HC08AZ32 282 Programmable Interrupt Timer (PIT)
4-pit
MOTOROLA
Programmable Interrupt Timer (PIT) I/O registers
I/O registers
The following I/O registers control and monitor operation of the PIT: * * * PIT status and control register (PSC) PIT counter registers (PCNTH:PCNTL) PIT counter modulo registers (PMODH:PMODL)
PIT status and control register (PSC)
The PIT status and control register does the following: * * * * * Enables PIT interrupt Flags PIT overflows Stops the PIT counter Resets the PIT counter Prescales the PIT counter clock
Bit 7 6 5 4 3 2 1 Bit 0
PSC $004B
Read: Write: Reset:
POF PIE 0
0 0 1
0 PSTOP PRST
0
0 PPS2
0 0
PPS1
0
PPS0
0
= Unimplemented
Figure 2. PIT Status and Control Register (TSC)
5-pit
MC68HC08AZ32 Programmable Interrupt Timer (PIT) 283
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Programmable Interrupt Timer (PIT)
POF -- PIT overflow flag bit This read/write flag is set when the PIT counter resets to $0000 after reaching the modulo value programmed in the PIT counter modulo registers. Clear POF by reading the PIT status and control register when POF is set and then writing a logic zero to POF. If another PIT overflow occurs before the clearing sequence is complete, then writing logic zero to POF has no effect. Therefore, a POF interrupt request cannot be lost due to inadvertent clearing of POF. Reset clears the POF bit. Writing a logic one to POF has no effect. 1 = PIT counter has reached modulo value 0 = PIT counter has not reached modulo value PIE -- PIT overflow interrupt enable bit This read/write bit enables PIT overflow interrupts when the POF bit becomes set. Reset clears the PIE bit. 1 = PIT overflow interrupts enabled 0 = PIT overflow interrupts disabled PSTOP -- PIT STOP bit This read/write bit stops the PIT counter. Counting resumes when PSTOP is cleared. Reset sets the PSTOP bit, stopping the PIT counter until software clears the PSTOP bit. 1 = PIT counter stopped 0 = PIT counter active
NOTE:
Do not set the PSTOP bit before entering wait mode if the PIT is required to exit wait mode.
PRST -- PIT reset bit Setting this write-only bit resets the PIT counter and the PIT prescaler. Setting PRST has no effect on any other registers. Counting resumes from $0000. PRST is cleared automatically after the PIT counter is reset and always reads as logic zero. Reset clears the PRST bit. 1 = Prescaler and PIT counter cleared 0 = No effect
NOTE:
Setting the PSTOP and PRST bits simultaneously stops the PIT counter at a value of $0000.
MC68HC08AZ32 284 Programmable Interrupt Timer (PIT)
6-pit
MOTOROLA
Programmable Interrupt Timer (PIT) I/O registers
PPS[2:0] -- Prescaler select bits These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as Table 2 shows. Reset clears the PPS[2:0] bits. Table 2. Prescaler selection
PS[2:0] 000 001 010 011 100 101 110 111 PIT clock source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 Internal Bus Clock / 64
PIT counter registers (PCNTH:PCNTL)
The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter. Reading the high byte (PCNTH) latches the contents of the low byte (PCNTL) into a buffer. Subsequent reads of PCNTH do not affect the latched PCNTL value until PCNTL is read. Reset clears the PIT counter registers. Setting the PIT reset bit (PRST) also clears the PIT counter registers.
NOTE:
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL retains the value latched during the break.
7-pit
MC68HC08AZ32 Programmable Interrupt Timer (PIT) 285
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Programmable Interrupt Timer (PIT)
Bit 15 PCNTH $004C Read: Write: Reset: 0
14
13
12
11
10
9
Bit 8
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
Bit 7
PCNTL $004D Read: Write: 0 Reset:
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Bit 7
0
0
0
0
0
0
0
= Unimplemented
Figure 3. PIT counter registers (PCNTH:PCNTL)
PIT Counter modulo registers (PMODH:PMODL)
The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value, the overflow flag (POF) becomes set, and the PIT counter resumes counting from $0000 at the next clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers.
Bit 15 14 13 12 11 10 9 Bit 8
PMODH $004E
Read:
Bit 15
Write: Reset: 1
14
1
13
1
12
1
11
1
10
1
9
1
Bit 8
1
Bit 7
PMODL $004F Read:
6 6
1
5 5
1
4 4
1
3 3
1
2 2
1
1 1
1
Bit 0 Bit 0
1
Bit 7
Write: Reset: 1
Figure 4. PIT Counter modulo registers (TMODH:TMODL)
NOTE:
MC68HC08AZ32 286
Reset the PIT counter before writing to the PIT counter modulo registers.
8-pit
Programmable Interrupt Timer (PIT)
MOTOROLA
Analog-to-Digital Converter (ADC) ADC
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 ADC port I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Accuracy and precision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 ADC analog power pin (VDDAREF) . . . . . . . . . . . . . . . . . . . . . . . 293 ADC analog ground pin (AVSS/VREFL) . . . . . . . . . . . . . . . . . . . . 293 ADC voltage reference pin (VREFH) . . . . . . . . . . . . . . . . . . . . . . 293 ADC voltage in (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 ADC status and control register (ADSCR) . . . . . . . . . . . . . . . . . . 294 ADC data register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 ADC clock register (ADCLKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
1-adc
MC68HC08AZ32 Analog-to-Digital Converter (ADC) 287
MOTOROLA
Analog-to-Digital Converter (ADC)
Introduction
This section describes the Analog to Digital Converter. The ADC is an eight bit analog to digital converter.
Features
Features of the ADC Module include the following: * * * * * * 8 or 15 channels with multiplexed input Linear successive approximation 8 bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock
MC68HC08AZ32 288 Analog-to-Digital Converter (ADC)
2-adc
MOTOROLA
Analog-to-Digital Converter (ADC) Functional description
Functional description
Eight or fifteen ADC channels are available for sampling external sources at pins PTD6/TACLK-PTD0 and PTB7/ATD7-PTB0/ATD0. An analog multiplexer allows the single ADC converter to select one ADC channel as ADC Voltage IN (ADCVIN). ADCVIN is converted by the successive approximation register based counter. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 1.
INTERNAL DATA BUS READ DDRB WRITE DDRB RESET WRITE PTB DDRBx/DDRDx PTBx/PTDx DISABLE
PTBx/PTDx (ADC Channel x)
READ PTB/PTD
DISABLE ADC DATA REGISTER
CONVERSION INTERRUPT COMPLETE LOGIC
ADC
ADC VOLTAGE IN ADCH[4:0] (ADVIN) CHANNEL SELECT
AIEN
COCO ADC CLOCK CGMXCLK BUS CLOCK
CLOCK GENERATOR
ADIV[2:0]
ADICLK
Figure 1. ADC block diagram
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Analog-to-Digital Converter (ADC)
ADC port I/O pins PTD6/TACLK-PTD0 and PTB7/ATD7-PTB0/ATD0 are general purpose I/O pins that share with the ADC channels. The Channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic zero.
NOTE:
Do not use ADC channels ATD14 or ATD12 when using the PTD6/TACLK or PTD4/TBLCK pins as the clock inputs for the 16-bit Timers.
Voltage conversion
When the input voltage to the ADC equals to VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals to AVSS/VREFL, the ADC converts it to $00. Input voltages between VREFH and AVSS/VREFL is a straight-line linear conversion. Conversion accuracy of all other input voltages is not guaranteed. Current injection on unused pins can also cause conversion inaccuracies.
NOTE:
Conversion time
Input voltage should not exceed the analog supply voltages.
Conversion starts after a write to the ADSCR. Conversion time in terms of the number of bus cycles is a function of oscillator frequency, bus frequency, and ADIV prescaler bits. For example, with oscillator frequency of 4MHz, bus frequency of 8MHz and ADC clock frequency of 1MHz, one conversion will take between 16 ADC and 17 ADC clock cycles or between 16 and 17 s in this case. There will be 128 bus cycles between each conversion. Sample rate is approximately 60kHz.
Conversion time =
16-17 ADC cycles ADC frequency
# Bus cycles = Conversion time x Bus frequency
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Analog-to-Digital Converter (ADC) Interrupts
Continuous conversion
In the continuous conversion mode, the ADC Data Register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and will stay set for the next several conversions until the next write of the ADC status and control register or the next read of the ADC data register.
Accuracy and precision
The conversion process is monotonic and has no missing codes.
Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic zero. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
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Analog-to-Digital Converter (ADC)
Low power modes
The WAIT and STOP instruction can put the MCU in low power consumption standby modes.
WAIT mode
The ADC continues normal operation during WAIT mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH[4:0] bits in the ADC Status and Control Register before executing the WAIT instruction.
STOP mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
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Analog-to-Digital Converter (ADC) I/O signals
I/O signals
The ADC module has 8 or 15 I/O that are shared with Port B and Port D.
ADC analog power pin (VDDAREF)
The ADC analog portion uses as its power pin. Connect the VDDAREF pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results.
NOTE:
Route VDDAREF carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. VDDAREF must be present for operation of he ADC.
ADC analog ground pin (AVSS/VREFL)
The ADC analog portion uses AVSS/VREFL as its ground pin. Connect the AVSS/VREFL pin to the same voltage potential as VSS.
ADC voltage reference pin (VREFH)
VREFH is the reference voltage for the ADC.
ADC voltage in (ADVIN)
ADVIN is the input voltage signal from one of the 8 or 15 ADC channels to the ADC module.
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Analog-to-Digital Converter (ADC)
I/O registers
The following I/O registers control and monitor operation of the ADC: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADCLK)
ADC status and control register (ADSCR)
The following paragraphs describe the function of the ADC Status and Control Register.
Bit 7
6
5
4
3
2
1
Bit 0
ADSCR $0038
Read: Write: Reset:
COCO AIEN R
0 0 0 1 1 1 1 1
ADCO
CH4
CH3
CH2
CH1
CH0
Figure 2. ADC status and control register
COCO -- Conversions complete When AIEN bit is a logic zero, the COCO is a read only bit which is set each time a conversion is completed except in the continuous conversion mode where it is set after the first conversion. This bit is cleared whenever the ADC Status and Control Register is written or whenever the ADC Data Register is read. If AIEN bit is a logic one, the COCO is a read bit which selects the CPU to service the ADC interrupt request. Reset clears this bit. 1 = conversion completed (AIEN=0) or CPU interrupt enabled (AIEN=1) 0 = conversion not completed (AIEN=0) or CPU interrupt enabled (AIEN=1)
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Analog-to-Digital Converter (ADC) I/O registers
AIEN -- ADC interrupt enable When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the Data Register is read or the Status/Control register is written. Reset clears AIEN bit. 1 = ADC Interrupt enabled 0 = ADC Interrupt disabled ADCO -- ADC continuous conversion When set, the ADC will continuously convert samples and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = continuous ADC conversion 0 = one ADC conversion ADCH[4:0] -- ADC channel select bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of the ADC channels. The channels are detailed in the following table. Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 1. The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used.
NOTE:
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.
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Analog-to-Digital Converter (ADC)
Table 1. Mux Channel Select
ADCH4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 ADCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Input Select PTB0/ATD0 PTB1/ATD1 PTB2/ATD2 PTB3/ATD3 PTB4/ATD4 PTB5/ATD5 PTB6/ATD6 PTB7/ATD7 PTD0 PTD1 PTD2 PTD3 PTD4/TBLCK PTD5 PTD6/TACLK Unused (see Note 1) Unused (see Note 1) 1 0 1 0 1 Reserved Unused (see Note 1) VREFH (see Note 2) VSSA/VREFL (see Note 2) [ADC power off]
Range 01111 ($0F) to 11010 ($1A) 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1
NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.
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Analog-to-Digital Converter (ADC) I/O registers
ADC data register (ADR)
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Bit 7
6
5
4
3
2
1
Bit 0
ADR $0039
Read: Write: Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3. ADC data register
ADC clock register (ADCLKR)
This register selects the clock frequency for the ADC
Bit 7
6
5
4
3
2
1
Bit 0
ADCLK $003A
Read:
0 ADIV2 ADIV1
0
0
0
0
ADIV0
0
ADICLK
0 0 0 0 0
Write: Reset: 0
= Unimplemented
Figure 4. ADC clock register
ADIV2:ADIV0 -- ADC clock prescaler bits ADIV2, ADIV1and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 2 shows the available clock configurations. The ADC clock should be set to approximately 1MHz. cgmxclk or bus frequency 1MHz = ------------------------------------------------------------ADIV [ 2:0 ]
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Table 2. ADC clock divide ratio
ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC input clock /1 ADC input clock / 2 ADC input clock / 4 ADC input clock / 8 ADC input clock / 16
X = don't care
ADICLK -- ADC input clock select ADICLK selects either bus clock or cgmxclk as the input clock source to generate the internal ADC clock. Reset selects cgmxclk as the ADC clock source. If the external clock (cgmxclk) is equal or greater than 1MHz, cgmxclk can be used as the clock source for the ADC. If cgmxclk is less than 1MHz, use the PLL generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1MHz, correct operation can be guaranteed. See Conversion time on page 290. 1 = Internal bus clock 0 = External clock (cgmxclk)
NOTE:
During the conversion process, changing the ADC clock will result in an incorrect conversion.
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Keyboard Module (KB) Keyboard Module
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Keyboard status and control register (KBSCR) . . . . . . . . . . . . . . 303 Keyboard interrupt enable register (KBIER) . . . . . . . . . . . . . . . . . 304 Keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . . 305
Introduction
The keyboard module provides five independently maskable external interrupt pins.
Features
Features of the keyboard module include the following: * * Five Keyboard Interrupt Pins and Interrupt Masks Selectable triggering sensitivity
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Keyboard Module (KB)
Functional description
Writing to the KBIE4-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port G or port H pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its pull-up device. A logic zero applied to a keyboard interrupt pin can latch a keyboard interrupt request. The keyboard interrupt latch becomes set when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering sensitivity of the keyboard interrupt latch. * If the keyboard interrupt latch is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the former pin while it is low. If the keyboard interrupt latch is edge- and level-sensitive, an interrupt request is latched as long as any keyboard pin is low.
*
INTERNAL BUS
PTG4/ KBD4 To pullup enable KB4IE
VECTOR FETCH DECODER VDD D CLR Q SYNCHRONIZER KEYBOARD INTERRUPT LATCH KEYBOARD INTERRUPT REQUEST ACKK
CK
PTG0/ KBD0 To pullup enable KB0IE
IMASKK
MODEK
Figure 5. Keyboard module block diagram
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Keyboard Module (KB) Functional description
Table 1. KB I/O register summary
Register Name Keyboard Status/Control R: Register (KBSCR) W: Reset Keyboard Interrupt Control R: Register (KBICR) W: Reset Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 0 0 0 0 0 0 0 0 1 Bit 0 Addr.
IMASK MODE $001B K K 0 0
KB4IE KB3IE KB2IE KB1IE KB0IE $0021 0 0 0 0 0
0
0
0
= Unimplemented
The MODEK bit in the keyboard status and control register controls the triggering sensitivity of the keyboard interrupt latch. If the MODEK bit is set, the keyboard interrupt pins are both falling-edge- and low-level-sensitive, and both of the following actions must occur to clear the keyboard interrupt latch: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt latch. Writing to the ACKK bit can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFD2 and $FFD3. Return of all enabled keyboard interrupt pins to logic one -- As long as any enabled keyboard interrupt pin is at logic zero, the keyboard interrupt latch remains set.
*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic one may occur in any order. The interrupt request remains pending as long as any enabled keyboard interrupt pin is at logic zero.
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Keyboard Module (KB)
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt latch. Reset clears the keyboard interrupt latch and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic zero. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBxIE) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic zero for software to read the pin.
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Keyboard Module (KB) I/O Registers
I/O Registers
The following registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
Keyboard status and control register (KBSCR)
The keyboard status and control register performs the following functions: * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard latch triggering sensitivity
Bit 7 6 5 4 3 2 1 Bit 0
KBSCR $001B
Read: Write: Reset:
0
0
0
0
KEYF
0 IMASKK MODEK ACKK
0
0
0
0
0
0
0
0
= Unimplemented
Figure 6. Keyboard status and control register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as logic zeros. KEYF -- Keyboard flag bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending
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Keyboard Module (KB)
ACKK -- Keyboard acknowledge bit Writing a logic one to this read/write bit clears the keyboard interrupt latch. ACKK always reads as logic zero. Reset clears ACKK. IMASKK -- Keyboard interrupt mask bit Writing a logic one to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests disabled 0 = Keyboard interrupt requests enabled MODEK -- Keyboard triggering sensitivity bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
Keyboard interrupt enable register (KBIER)
The keyboard interrupt enable register enables or disables each port G or port H pin to operate as a keyboard interrupt pin.
Bit 7 KBIER $0021 Read: Write: Reset 0 0
6 0
5 0
4 KBIE4
3 KBIE3 0
2 KBIE2 0
1 KBIE1 0
Bit 0 KBIE0 0
0
0
0
= Unimplemented
Figure 7. Keyboard interrupt enable register (KBIER) KBIE4:KBIE0 -- Keyboard interrupt enable bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = Pin enabled as keyboard interrupt pin 0 = Pin not enabled as keyboard interrupt pin
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Keyboard Module (KB) Keyboard module during break interrupts
Keyboard module during break interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing during the break state to the keyboard acknowledge bit (ACKK) in the keyboard status and control register has no effect. See Keyboard status and control register (KBSCR) on page 303.
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Keyboard Module (KB)
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I/O Ports I/O Ports
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Port A Data Register (PTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 309 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Port B data register (PTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 312 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Port C data register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 315 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Port D data register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Data direction register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . . 318 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Port E data register (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Data direction register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . 322 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Port F data register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Data direction register F (DDRF) . . . . . . . . . . . . . . . . . . . . . . . . . 325 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Port G data register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Data direction register G (DDRG) . . . . . . . . . . . . . . . . . . . . . . . . . 327 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Port H data register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Data direction register H (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . 329
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I/O Ports
Introduction
Forty-nine bidirectional input-output (I/O) pins form eight parallel ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Table 1. I/O port register summary
Register Name
Bit 7
6 PTA6 PTB6 0 PTD6
5 PTA5 PTB5 PTC5 PTD5
4 PTA4 PTB4 PTC4 PTD4
3 PTA3 PTB3 PTC3 PTD3
2 PTA2 PTB2 PTC2 PTD2
1 PTA1 PTB1 PTC1 PTD1
Bit 0
Addr.
Port A Data Register (PTA) PTA7 Port B Data Register (PTB) PTB7 Port C Data Register (PTC) 0
PTA0 $0000 PTB0 $0001 PTC0 $0002 PTD0 $0003
Port D Data Register (PTD) PTD7
Data Direction Register A (DDRA) DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 Data Direction Register B (DDRB) DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 Data Direction Register C (DDRC)MCLKEN 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006
Data Direction Register D (DDRD) DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 $0007 Port E Data Register (PTE) PTE7 Port F Data Register (PTF) Port G Data Register (PTG) Port H Data Register (PTH) 0 0 0 PTE6 PTF6 0 0 PTE5 PTF5 0 0 PTE4 PTF4 0 0 PTE3 PTF3 0 0 PTE2 PTF2 PTG2 0 PTE1 PTF1 PTG1 PTH1 PTE0 $0008 PTF0 $0009 PTG0 $000A PTH0 $000B
Data Direction Register E (DDRE) DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 $000C Data Direction Register F (DDRF) Data Direction Register G (DDRG) Data Direction Register H (DDRH) 0 0 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 $000D 0 0 0 0 0 0 0 0 DDRG2 DDRG1 DDRG0 $000E 0 DDRH1 DDRH0 $000F
MC68HC08AZ32 308 I/O Ports
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I/O Ports Port A
Port A
Port A is an 8-bit general-purpose bidirectional I/O port.
Port A Data Register (PTA)
The port A data register contains a data latch for each of the eight port A pins.
Bit 7 6 5 4 3 2 1 Bit 0
PTA $0000
Read:
PTA7
Write: Reset:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by reset
Figure 1. Port A data register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.
Data direction register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer.
Bit 7 6 5 4 3 2 1 Bit 0
DDRA $0004
Read:
DDRA7
Write: Reset: 0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Figure 2 Data direction register A (DDRA) DDRA[7:0] -- Data direction register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
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I/O Ports
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1.
Figure 3 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004) RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 3. Port A I/O Circuit When bit DDRAx is a logic one, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic zero, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 2 summarizes the operation of the port A pins. Table 2. Port A pin functions
DDRA Bit PTA Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRA Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0]
DDRA[7:0] DDRA[7:0]
MC68HC08AZ32 310 I/O Ports
4-io
MOTOROLA
I/O Ports Port B
Port B
Port B is an 8-bit special function port that shares all of its pins with the analog to digital convertor.
Port B data register (PTB)
The port B data register contains a data latch for each of the eight port B pins.
Bit 7 6 5 4 3 2 1 Bit 0
PTB $0001
Read:
PTB7
Write: Reset:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
ALTERNATE FUNCTIONS
ATD7
ATD6
ATD5
ATD4
ATD3
ATD2
ATD1
ATD0
Figure 4. Port B data register (PTB) PTB[7:0] -- Port B data bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. ATD[7:0] -- ADC channels
NOTE:
PTB7/ATD7- PTB0/ATD0 are eight analog to digital convertor channels. The ADC channel select bits, CH[4:0], determine whether the PTB7/ATD7-PTB0/ATD0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be zero if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. Data direction register B (DDRB) does not affect the data direction of port B pins that are being used by the ADC. However, the DDRB bits always determine whether reading port B returns the states of the latches or logic 0.
5-io
MC68HC08AZ32 I/O Ports 311
MOTOROLA
I/O Ports
Data direction register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer.
Bit 7 DDRB $0005 Read: 6 5 4 3 2 1 Bit 0
DDRB7
Write: Reset: 0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
DDRB1
0
DDRB0
0
Figure 5. Data direction register B (DDRB) DDRB[7:0] -- Data direction register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1.
Figure 6 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005) RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
Figure 6. Port B I/O circuit
MC68HC08AZ32 312 I/O Ports
6-io
MOTOROLA
I/O Ports Port B
When bit DDRBx is a logic one, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 3 summarizes the operation of the port B pins. Table 3. Port B pin functions
DDRB Bit PTB Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRB Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTB Read Pin PTB[7:0] Write PTB[7:0](3) PTB[7:0]
DDRB[7:0] DDRB[7:0]
7-io
MC68HC08AZ32 I/O Ports 313
MOTOROLA
I/O Ports
Port C
Port C is a 6-bit general-purpose bidirectional I/O port.
Port C data register (PTC)
The port C data register contains a data latch for each of the six port C pins.
Bit 7 6 5 4 3 2 1 Bit 0
PTC $0002
Read: Write: Reset:
0
0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Unaffected by reset
ALTERNATE FUNCTIONS
= Unimplemented
MCLK
Figure 7. Port C data register (PTC) PTC[5:0] -- Port C data bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. MCLK -- T12 System Clock The system clock is driven out of PTC2 when enabled by MCLKEN.
MC68HC08AZ32 314 I/O Ports
8-io
MOTOROLA
I/O Ports Port C
Data direction register C (DDRC)
Data direction register C determines whether each port C pin is an input or an output. Writing a logic one to a DDRC bit enables the output buffer for the corresponding port C pin; a logic zero disables the output buffer.
Bit 7 6 5 4 3 2 1 Bit 0
DDRC $0006
Read: MCLKE Write: Reset:
0 DDRC5
0 0
N
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
= Unimplemented
Figure 8. Data direction register C (DDRC) MCLKEN -- MCLK enable bit This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, PTC2 is under the control of MCLKEN. Reset clears this bit. 1 = MCLK output enabled 0 = MCLK output disabled DDRC[5:0] -- Data direction register C bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1.
Figure 9 shows the port C I/O logic.
9-io
MC68HC08AZ32 I/O Ports 315
MOTOROLA
I/O Ports
.
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006) RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 9. Port C I/O circuit When bit DDRCx is a logic one, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic zero, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 4 summarizes the operation of the port C pins. Table 4. Port C pin functions
Bit Value PTC Bit I/O Pin Mode Accesses to DDRC Read/Write 0 1 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTC Read Pin 0 Pin PTC[5:0] Write PTC2
2 2 X(1) X
Input, Hi-Z Output Input, Hi-Z(2) Output
DDRC[7] DDRC[7] DDRC[5:0] DDRC[5:0]
--
PTC[5:0](3) PTC[5:0]
MC68HC08AZ32 316 I/O Ports
10-io
MOTOROLA
I/O Ports Port D
Port D
Port D is an 8-bit general-purpose I/O port.
Port D data register (PTD)
Port D is an 8 -bit special function port that shares seven of it's pins with the analog to digital converter and two with the TIMA and TIMB modules.
Bit 7 6 5 4 3 2 1 Bit 0
PTD $0003
Read:
PTD7
Write: Reset:
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset
Alternate Functions
R
ATD14/ TACLK
ATD13
ATD12/ TBCLK
ATD11
ATD10
ATD9
ATD8
Figure 10. Port D data register (PTD) PTD[7:0] -- Port D data bits PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the control of the corresponding bit in data direction register D. Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer ATD[14:8] -- ADC channel status bits PTD6/ATD14/TACLK-PTD0/ATD8 are seven of the 15 analog-to-digital converter channels. The ATD channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK-PTD0/ATD8 pins are ADC channels or general purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise the data will reflect the value in the data latch.
NOTE:
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the TIMA or TIMB. However, the
11-io
MC68HC08AZ32 I/O Ports 317
MOTOROLA
I/O Ports
DDRD bits always determine whether reading port D returns the states of the latches to logic 0.
TACLK/TBCLK -- Timer clock input The PTD6/TACLK pin is the external clock input for the TIMA. The PTD4/TBCLK pin is the external clock input for the TIMB.The prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBCLK as the TIM clock input (see TIMA channel status and control registers (TASC0-TASC3) on page 250 and TIMB status and control register (TBSC) on page 270). When not selected as the TIM clock, PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O. While TACLK/TBCLK are selected, corresponding DDRD bits have no effect.
Data direction register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer.
Bit 7 6 5 4 3 2 1 Bit 0
DDRD $0007
Read:
DDRD7
Write: Reset: 0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Figure 11. Data direction register D (DDRD) DDRD[7:0] -- Data direction register D bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1.
Figure 12 shows the port D I/O logic. When bit DDRDx is a logic one, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic zero, reading address $0003
MC68HC08AZ32 318 I/O Ports
12-io
MOTOROLA
I/O Ports Port D
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007) RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
Figure 12. Port D I/O circuit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 5 summarizes the operation of the port D pins. Table 5. Port D pin functions
DDRD Bit PTD Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRD Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTD Read Pin PTD[7:0] Write PTD[7:0](3) PTD[7:0]
DDRD[7:0] DDRD[7:0]
13-io
MC68HC08AZ32 I/O Ports 319
MOTOROLA
I/O Ports
Port E
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI) and four of its pins with the serial peripheral interface module (SPI).
Port E data register (PTE)
The port E data register contains a data latch for each of the eight port E pins.
Bit 7 6 5 4 3 2 1 Bit 0
PTE $0008
Read:
PTE7
Write: Reset: Alternate SPSCK Function:
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by reset
MOSI
MISO
SS
TACH1
TACH0
RxD
TxD
Figure 13. Port E data register (PTE) PTE[7:0] -- Port E data bits PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. SPSCK -- SPI serial clock The PTE7/SPSCK pin is the serial clock input of a SPI slave module and serial clock output of a SPI master modules. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O. MOSI -- Master Out/Slave In The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTE6/MOSI pin is available for general-purpose I/O. See SPI control register (SPCR) on page 223.
MC68HC08AZ32 320 I/O Ports
14-io
MOTOROLA
I/O Ports Port E
MISO -- Master In/Slave Out The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. See SPI control register (SPCR) on page 223. SS -- Slave Select The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTE4/SS pin is available for general-purpose I/O. See SPI control register (SPCR) on page 223. When the SPI is enabled as a slave, the DDRF0 bit in data direction register E (DDRE) has no effect on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 6.
TACH[1:0] -- Timer A channel I/O bits The PTE3/TACH1-PTE2/TACH0 pins are the TIMA input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1-PTE2/TACH0 pins are timer channel I/O pins or general-purpose I/O pins. See TIMA channel status and control registers (TASC0-TASC3) on page 250.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIMA. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 6.
RxD -- SCI Receive data input The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See SCI control register 1 (SCC1) on page 181.
15-io
MC68HC08AZ32 I/O Ports 321
MOTOROLA
I/O Ports
TxD -- SCI transmit data output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See SCI Control Register 2 (SCC2) on page 184.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 6.
Data direction register E (DDRE)
Data direction register E determines whether each port E pin is an input or an output. Writing a logic one to a DDRE bit enables the output buffer for the corresponding port E pin; a logic zero disables the output buffer.
Bit 7 6 5 4 3 2 1 Bit 0
DDRE $000C
Read:
DDRE7
Write: Reset: 0
DDRE6
0
DDRE5
0
DDRE4
0
DDRE3
0
DDRE2
0
DDRE1
0
DDRE0
0
Figure 14. Data direction register E (DDRE) DDRE[7:0] -- Data direction register E bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1.
Figure 15 shows the port E I/O logic. When bit DDREx is a logic one, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic zero, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 6 summarizes the operation of the port E pins.
MC68HC08AZ32 322 I/O Ports
16-io
MOTOROLA
I/O Ports Port E
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C) RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 15. Port E I/O circuit Table 6. Port E pin functions
DDRE Bit PTE Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRE Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTE Read Pin PTE[7:0] Write PTE[7:0](3) PTE[7:0]
DDRE[7:0] DDRE[7:0]
17-io
MC68HC08AZ32 I/O Ports 323
MOTOROLA
I/O Ports
Port F
Port F is a 7-bit special function port that shares four of its pins with the timer interface module (TIMA-6) and two of its pins with the timer interface module (TIMB)).
Port F data register (PTF)
The port F data register contains a data latch for each of the seven port F pins.
Bit 7 6 PTF6 Write: Reset: Alternate Function: Unaffected by reset 5 PTF5 4 PTF4 3 PTF3 2 PTF2 1 PTF1 Bit 0 PTF0
PTF $0009
Read:
0
TBCH1
= Unimplemented
TBCH0
TACH5
TACH4
TACH3
TACH2
Figure 16. Port F data register (PTF) PTF[6:0] -- Port F data bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0]. TACH[5:2] -- Timer A channel I/O bits The PTF3/TACH5-PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF3/TACH5-PTF0/TACH2 pins are timer channel I/O pins or general-purpose I/O pins.
MC68HC08AZ32 324 I/O Ports
18-io
MOTOROLA
I/O Ports Port F
TBCH[1:0] -- Timer B channel I/O bits The PTF5/TBCH1-PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4/TBCH0 pins are timer channel I/O pins or general purpose I/O pins. See TIMB status and control register (TBSC) on page 270.
NOTE:
Data direction register F(DDRF) does not affect the data direction of port F pins that are being used by TIMA and TIMB. However, the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins. See Table 7.
Data direction register F (DDRF)
Data direction register F determines whether each port F pin is an input or an output. Writing a logic one to a DDRF bit enables the output buffer for the corresponding port F pin; a logic zero disables the output buffer.
Bit 7 6 5 4 3 2 1 Bit 0
DDRF $000D
Read: Write: Reset:
0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
0 0 0 0 0 0 0
= Unimplemented
Figure 17. Data direction register F (DDRF) DDRF[6:0] -- Data direction register F bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input
NOTE:
Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1.
19-io
MC68HC08AZ32 I/O Ports 325
MOTOROLA
I/O Ports
Figure 18 shows the port F I/O logic.
READ DDRF ($000D)
INTERNAL DATA BUS
WRITE DDRF ($000D) RESET WRITE PTF ($0009) PTFx PTFx DDRFx
READ PTF ($0009)
Figure 18. Port F I/O circuit When bit DDRFx is a logic one, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic zero, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 7 summarizes the operation of the port F pins. Table 7. Port F pin functions
DDRF Bit PTF Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRF Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTF Read Pin PTF[6:0] Write PTF[6:0](3) PTF[6:0]
DDRF[6:0] DDRF[6:0]
MC68HC08AZ32 326 I/O Ports
20-io
MOTOROLA
I/O Ports Port G
Port G
Port G is a 3-bit general-purpose bidirectional I/O port. Port G data register (PTG) The port G data register contains a data latch for each of the three port G pins.
Bit 7 Read: PTG $000A Write: Reset: Alternate Function = Unimplemented Unaffected by reset 6 5 4 3 2 1 Bit 0
0
0
0
0
0 PTG2 PTG1 PTG0
KBD2
KBD1
KBD0
Figure 19. Port G data register (PTG) PTG[2:0] -- Port G Data Bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding bit in data direction register G. Reset has no effect on port G data. KBD[2:0] -- Keyboard Inputs The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register (KBICR), enable the port G pins as external interrupt pins. See Keyboard Module (KB) on page 299. Data direction register G (DDRG) Data direction register G determines whether each port G pin is an input or an output. Writing a logic one to a DDRG bit enables the output buffer for the corresponding port G pin; a logic zero disables the output buffer.
Bit 7 DDRG $000E Read: Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 6 5 4 3 2 1 Bit 0
0
0
0
0
0 DDRG2 DDRG1 DDRG0
Figure 20. Data direction register G (DDRG)
21-io
MC68HC08AZ32 I/O Ports 327
MOTOROLA
I/O Ports
DDRG[2:0] -- Data direction register G bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input
NOTE:
Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1.
Figure 21 shows the port G I/O logic.
READ DDRG ($000E)
INTERNAL DATA BUS
WRITE DDRG ($000E) RESET WRITE PTG ($000A) PTGx PTGx DDRGx
READ PTG ($000A)
Figure 21. Port G I/O circuit When bit DDRGx is a logic one, reading address $000A reads the PTGx data latch. When bit DDRGx is a logic zero, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data.
MC68HC08AZ32 328 I/O Ports
22-io
MOTOROLA
I/O Ports Port H
Port H
Port H is a 2-bit general-purpose bidirectional I/O port. Port H data register (PTH) The port H data register contains a data latch for each of the two port H pins.
Bit 7 Read: PTH $000B Write: Reset: Alternate Function = Unimplemented Unaffected by reset 6 5 4 3 2 1 Bit 0
0
0
0
0
0 PTH1 PTH0
KBD4
KBD3
Figure 22. Port H data register (PTH) PTH[1:0] -- Port H data bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding bit in data direction register H. Reset has no effect on port G data. KBD[4:3] -- Keyboard inputs The keyboard interrupt enable bits, KBIE[4:3], in the keyboard interrupt control register (KBICR), enable the port H pins as external interrupt pins. See Keyboard Module (KB) on page 299 Data direction register H (DDRH) Data direction register H determines whether each port H pin is an input or an output. Writing a logic one to a DDRH bit enables the output buffer for the corresponding port H pin; a logic zero disables the output buffer.
Bit 7 DDRH $000F Read: Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 6 5 4 3 2 1 Bit 0
0
0
0
0
0
0 DDRH1 DDRH0
Figure 23. Data direction register H (DDRH)
23-io
MC68HC08AZ32 I/O Ports 329
MOTOROLA
I/O Ports
DDRH[1:0] -- Data direction register H bits These read/write bits control port H data direction. Reset clears DDRH[1:0], configuring all port H pins as inputs. 1 = Corresponding port H pin configured as output 0 = Corresponding port H pin configured as input
NOTE:
Avoid glitches on port H pins by writing to the port H data register before changing data direction register H bits from 0 to 1.
Figure 24 shows the port H I/O logic.
READ DDRH ($000E)
INTERNAL DATA BUS
WRITE DDRH ($000E) RESET WRITE PTH ($000A) PTHx PTGx DDRHx
READ PTH ($000A)
Figure 24. Port H I/O circuit When bit DDRHx is a logic one, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic zero, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data.
MC68HC08AZ32 330 I/O Ports
24-io
MOTOROLA
msCAN08 Controller (msCAN08) msCAN08
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 External pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Message storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Receive structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Transmit structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Interrupt acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 msCAN08 internal sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Soft Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Power Down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 CPU WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Programmable wake-up function . . . . . . . . . . . . . . . . . . . . . . . . . 350 Timer link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Clock system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Programmer's model of message storage . . . . . . . . . . . . . . . . . . . . 355 Message Buffer outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Identifier registers (IDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Data length register (DLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Data segment registers (DSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Transmit buffer priority registers (TBPR) . . . . . . . . . . . . . . . . . . . 359 Programmer's model of control registers . . . . . . . . . . . . . . . . . . . . . 360 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 msCAN08 module control register (CMCR0) . . . . . . . . . . . . . . . . 361 msCAN08 module control register (CMCR1) . . . . . . . . . . . . . . . . 363 msCAN08 bus timing register 0 (CBTR0) . . . . . . . . . . . . . . . . . . . 364
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msCAN08 Controller (msCAN08)
msCAN08 bus timing register 1 (CBTR1) . . . . . . . . . . . . . . . . . . . 365 msCAN08 receiver flag register (CRFLG). . . . . . . . . . . . . . . . . . . 366 msCAN08 Receiver Interrupt Enable Register (CRIER) . . . . . . . . 369 msCAN08 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . 370 msCAN08 Transmitter Control Register (CTCR) . . . . . . . . . . . . . 371 msCAN08 Identifier Acceptance Control Register (CIDAC) . . . . . 372 msCAN08 Receive Error Counter (CRXERR) . . . . . . . . . . . . . . . 373 msCAN08 Transmit Error Counter (CTXERR) . . . . . . . . . . . . . . . 374 msCAN08 Identifier Acceptance Registers (CIDAR0-3) . . . . . . . . 374 msCAN08 Identifier Mask Registers (CIDMR0-3). . . . . . . . . . . . . 375
Introduction
The msCAN08 is the specific implementation of the Motorola Scalable CAN (msCAN) concept targeted for the Motorola M68HC08 Microcontroller family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September 1991. The CAN protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. msCAN08 utilizes an advanced buffer arrangement resulting in a predictable real-time behaviour and simplifies the application software.
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msCAN08 Controller (msCAN08) Features
Features
The basic features of the msCAN08 are as follows: * * Modular architecture Implementation of the CAN protocol - Version 2.0A/B - Standard and extended data frames. - 0 - 8 bytes data length. - Programmable bit rate up to 1 Mbps1. * * * * * * * * * * Support for remote frames. Double buffered receive storage scheme. Triple buffered transmit storage scheme with internal prioritization using a `local priority' concept. Flexible maskable identifier filter supports alternatively one full size extended identifier filter or two 16 bit filters or four 8 bit filters. Programmable wake-up functionality with integrated low-pass filter. Programmable loop-back mode supports self-test operation. Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (Warning, Error Passive, Bus-Off). Programmable msCAN08 clock source either CPU bus clock or crystal oscillator output. Programmable link to on-chip Timer Interface Module (TIM) for time-stamping and network synchronization. Low power sleep mode.
1. Depending on the actual bit timing and the clock jitter of the PLL.
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msCAN08 Controller (msCAN08)
External pins
The msCAN08 uses 2 external pins, 1 input (RxCAN) and 1 output (TxCAN). The TxCAN output pin represents the logic level on the CAN: `0' is for a dominant state, and `1' is for a recessive state. A typical CAN system with msCAN08 is shown in Figure 1 below.
CAN station 1 MCU
CAN station 2 ........ CAN station n
CAN Controller (msCAN08)
TxCAN
RxCAN
Transceiver
CAN_H
CAN_L C A N - Bus Figure 1. The CAN system
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msCAN08 Controller (msCAN08) Message storage
Each CAN station is physically connected to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current needed for the CAN and has current protection, against defected CAN or defected stations.
Message storage
msCAN08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
Background
Modern application layer software is built under two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages. Such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. The internal message queue within any CAN node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. Above behaviour can not be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the Inter-Frame Sequence (IFS) in order to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message sending and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer, no buffer would then be ready for transmission and the bus would be released.
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msCAN08 Controller (msCAN08)
At least three transmit buffers are required to meet the first of above requirements under all circumstances. The msCAN08 has three transmit buffers. The second requirement calls for some sort of internal prioritization which the msCAN08 implements with the `local priority' concept described below.
Receive structures
The received messages are stored in a two stage input FIFO. The two message buffers are mapped using a `ping pong' arrangement into a single memory area (see Figure 2). While the background receive buffer (RxBG) is exclusively associated to the msCAN08, the foreground receive buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software as only one address area is applicable for the receive process. Both buffers have a size of 13 byte to store the CAN control bits, the identifier (standard or extended) and the data content (for details see Programmer's model of message storage on page 355). The Receiver Full flag (RXF) in the msCAN08 Receiver Flag Register (CRFLG) (see msCAN08 receiver flag register (CRFLG) on page 366) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with matching identifier this flag is set. After the msCAN08 successfully received a message into the background buffer it copies the content of RxBG into RxFG1, sets the RXF flag, and emits a receive interrupt to the CPU2. A new message which may follow immediately after the IFS field of the CAN frame - will be received into RxBG. The user's receive handler has to read the received message from RxFG and to reset the RXF flag in order to acknowledge the interrupt and to release the foreground buffer.
1. Only if the RXF flag is not set. 2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
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msCAN08 Controller (msCAN08) Message storage
An overrun conditions occurs when both, the foreground and the background receive message buffers are filled with correctly received messages and a further message is being received from the bus. The latter message will be discarded and an error interrupt with overrun indication will occur if enabled. The over-writing of the background buffer is independent of the identifier filter function. While in the overrun situation, the msCAN08 will stay synchronized to the CAN bus and is able to transmit messages but will discard all incoming messages.
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msCAN08 Controller (msCAN08)
CAN Receive / Transmit Engine
CPU08 Memory Mapped I/O
msCAN08
RxBG RxFG RXF
CPU08 Ibus
Tx0
TXE
PRIO Tx1 TXE
PRIO Tx2 TXE
PRIO Figure 2. User model for Message Buffer organization
NOTE:
msCAN08 will receive its own messages into the background receive buffer RxBG, but will not overwrite RxFG, and will not emit a receive interrupt, or acknowledge (ACK its own messages on the CAN bus. The
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msCAN08 Controller (msCAN08) Message storage
exception to this rule is that when in loop-back mode msCAN08 will treat its own messages exactly like all other incoming messages.
Transmit structures
The msCAN08 has a triple transmit buffer scheme in order to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 2. All three buffers have a 13 byte data structure similar to the outline of the receive buffers (see Programmer's model of message storage on page 355). An additional Transmit Buffer Priority Register (TBPR) contains an 8-bit so called "Local Priority" field (PRIO) (see Transmit buffer priority registers (TBPR) on page 359). In order to transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set Transmit Buffer Empty (TXE) Flag in the msCAN08 Transmitter Flag Register (CTFLG) (see msCAN08 Transmitter Flag Register (CTFLG) on page 370). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged as being ready for transmission by clearing the TXE flag. The msCAN08 will then schedule the message for transmission and will signal the successful transmission of the buffer by setting the TXE flag. A transmit interrupt will be emitted1 when TXE is set and can be used to drive the application software to re-load the buffer. In case more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the msCAN08 uses the "local priority" setting of the three buffers for prioritization. For this purpose every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority.
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also.
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msCAN08 Controller (msCAN08)
The internal scheduling process takes places whenever the msCAN08 arbitrates for the bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. As messages that are already under transmission can not be aborted, the user has to request the abort by setting the corresponding Abort Request Flag (ABTRQ) in the Transmission Control Register (CTCR). The msCAN08 will then grant the request if possible by setting the corresponding Abort Request Acknowledge (ABTAK) and the TXE flag in order to release the buffer and by emitting a transmit interrupt. The transmit interrupt handler software can tell from the setting of the ABTAK flag whether the message was actually aborted (ABTAK=1) or has been sent in the meantime (ABTAK=0).
Identifier acceptance filter
A very flexible programmable generic identifier acceptance filter has been introduced in order to reduce the CPU interrupt loading. The filter is programmable to operate in three different modes: * Single identifier acceptance filter to be applied to the full 29 bits of the identifier and to the following bits of the CAN frame: RTR, IDE, SRR. This mode implements a single filter for a full length CAN 2.0B compliant extended identifier. Double identifier acceptance filter to be applied to - the 11 bits of the identifier and the RTR bit of CAN 2.0A messages or - the 14 most significant bits of the identifier of CAN 2.0B messages. * Quadruple identifier acceptance filter to be applied to the first 8 bits of the identifier. This mode implements four independent filters for the first 8 bit of a CAN 2.0A compliant standard identifier.
*
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msCAN08 Controller (msCAN08) Interrupts
The Identifier Acceptance Registers (CIAR) defines the acceptable pattern of the standard or extended identifier (ID10 - ID0 or ID28 - ID0). Any of these bits can be marked `don't care' in the Identifier Mask Register (CIMR). ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2 ID7 ID6 IDR3 RTR ID3 ID10 IDR3 ID3
AM7 CIDMR0 AM0 AM7 CIDMR1 AM0 AM7 CIDMR2 AM0 AM7 CIDMR3 AM0 AC7 CIDAR0 AC0 AC7 CIDAR1 AC0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0
ID Accepted (Filter 0 Hit)
Figure 3. Single 32-bit maskable identifier acceptance filter The background buffer RxBG will be copied into the foreground buffer RxFG and the RxF flag will be set only in case of an accepted identifier (an identifier acceptance filter hit). A hit will also cause a receiver interrupt if enabled. A filter hit is indicated to the application software by a set RXF (Receive Buffer Full Flag, see msCAN08 receiver flag register (CRFLG) on page 366) and two bits in the Identifier Acceptance Control Register (see msCAN08 Identifier Acceptance Control Register (CIDAC) on page 372). These Identifier Hit Flags (IDHIT1-0) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. In case that more than one hit occurs (two or more filters match) the lower hit has priority.
Interrupts
The msCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for
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msCAN08 Controller (msCAN08)
ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2
ID7 ID6 IDR3 RTR ID3 ID10 IDR3 ID3
AM7 CIDMR0 AM0 AM7 CIDMR1 AM0 AC7 CIDAR0 AC0 AC7 CIDAR1 AC0
ID Accepted (Filter 0 Hit)
AM7 CIDMR2 AM0 AM7 CIDMR3 AM0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0
ID Accepted (Filter 1 Hit)
Figure 4. Dual 16-bit maskable acceptance filters details see msCAN08 receiver flag register (CRFLG) on page 366 to msCAN08 Transmitter Control Register (CTCR) on page 371): *
Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. Receive Interrupt: A message has been successfully received and loaded into the foreground receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF flag is set. Wake-Up Interrupt: An activity on the CAN bus occurred during msCAN08 internal sleep mode.
*
*
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msCAN08 Controller (msCAN08) Interrupts
ID28 IDR0 ID21 ID20 IDR1 ID15 ID14 IDR2 ID10 IDR0 ID3 ID2 IDR1 IDE ID10 IDR2
ID7 ID6 IDR3 RTR ID3 ID10 IDR3 ID3
AM7 CIDMR0 AM0 AC7 CIDAR0 AC0
ID Accepted (Filter 0 Hit)
AM7 CIDMR1 AM0 AC7 CIDAR1 AC0
ID Accepted (Filter 1 Hit)
AM7 CIDMR2 AM0 AC7 CIDAR2 AC0
ID Accepted (Filter 2 Hit)
AM7 CIDMR3 AM0 AC7 CIDAR3 AC0
ID Accepted (Filter 3 Hit)
Figure 5. Quadruple 8-bit maskable acceptance filters
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msCAN08 Controller (msCAN08)
*
Error Interrupt: An overrun, error or warning condition occurred. The Receiver Flag Register (CRFLG) will indicate one of the following conditions:
- Overrun: An overrun condition as described in Receive structures on page 336, has occurred. - Receiver Warning: The Receive Error Counter has reached the CPU Warning limit of 96. - Transmitter Warning: The Transmit Error Counter has reached the CPU Warning limit of 96. - Receiver Error Passive: The Receive Error Counter has exceeded the Error Passive limit of 127 and msCAN08 has gone to Error Passive state. - Transmitter Error Passive: The Transmit Error Counter has exceeded the Error Passive limit of 127 and msCAN08 has gone to Error Passive state. - Bus Off: The Transmit Error Counter has exceeded 255 and msCAN08 has gone to Bus Off state.
Interrupt acknowledge
Interrupts are directly associated with one or more status flags in either the msCAN08 Receiver Flag Register (CRFLG) or the msCAN08 Transmitter Control Register (CTCR). Interrupts are pending as long as one of the corresponding flags is set. The flags in above registers must be reset within the interrupt handler in order to handshake the interrupt. The flags are reset through writing a "1" to the corresponding bit position. A flag can not be cleared if the respective condition still prevails.
CAUTION:
Bit manipulation instructions (BSET) shall not be used to clear interrupt flags. The `OR' instruction is the appropriate way to clear selected flags.
Interrupt vectors
The msCAN08 supports four interrupt vectors as shown in Table 1. The vector addresses are dependent on the chip integration and to be defined. The relative interrupt priority is also integration dependent and to be defined.
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msCAN08 Controller (msCAN08) Interrupts
Table 1. msCAN08 interrupt vectors
Function
Wake-Up
Source
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF
Local Mask
WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE0 TXEIE1 TXEIE2
Global Mask
Error Interrupts
I Bit
Receive Transmit
RXF TXE0 TXE1 TXE2
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msCAN08 Controller (msCAN08)
Protocol violation protection
The msCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * * The receive and transmit error counters can not be written or otherwise manipulated. All registers which control the configuration of the msCAN08 can not be modified while the msCAN08 is on-line. The SFTRES bit in the msCAN08 Module Control Register (see msCAN08 module control register (CMCR1) on page 363) serves as a lock to protect the following registers: - msCAN08 Module Control Register 1 (CMCR1) - msCAN08 Bus Timing Register 0 and 1 (CBTR0, CBTR1) - msCAN08 Identifier Acceptance Control Register (CIDAC) - msCAN08 Identifier Acceptance Registers (CIDAR0-3) - msCAN08 Identifier Mask Registers (CIDMR0-3) * The TxCAN pin is forced to Recessive if the CPU goes into STOP mode.
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msCAN08 Controller (msCAN08) Low power modes
Low power modes
The msCAN08 has three modes with reduced power consumption compared to Normal Mode. In Sleep and Soft Reset Mode, power consumption is reduced by stopping all clocks except those to access the registers. In Power Down Mode, all clocks are stopped and no power is consumed. WAIT and STOP instruction put the MCU in low power consumption stand-by mode. Table 2 summarizes the combinations of msCAN08 and CPU modes. A particular combination of modes is entered for the given settings of the bits SLPAK and SFTRES. In Sleep and Soft Reset Mode, power consumption of the msCAN module is lower than in Normal Mode. In Power Down Mode, no power is consumed in the module and no registers can be accessed. For all modes, an msCAN wake-up interrupt can occur only if SLPAK = WUPIE = 1. While the CPU is in Wait Mode, the msCAN08 is operated as in Normal Mode. Table 2. msCAN08 vs CPU operating modes msCAN Mode Power Down Sleep Soft Reset Normal
1. `X' means don't care.
CPU Mode STOP SLPAK = X(1) SFTRES = X SLPAK = 1 SFTRES = 0 SLPAK = 0 SFTRES = 1 SLPAK = 0 SFTRES = 0 WAIT or RUN
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msCAN08 Controller (msCAN08)
msCAN08 internal sleep mode The CPU can request the msCAN08 to enter the low-power mode by asserting the SLPRQ bit in the Module Configuration Register (see Figure 6). The time when the msCAN08 will then enter Sleep Mode depends on its current activity: * * * if it is transmitting, it will continue to transmit until there is no more message to be transmitted, and then go into Sleep Mode if it is receiving, it will wait for the end of this message and then go into Sleep Mode if it is neither transmitting or receiving, it will immediately go into Sleep Mode
The application software must avoid to set up a transmission (by clearing one or more TXE flag(s)) and immediately request Sleep Mode (by setting SLPRQ). It will then depend on the exact sequence of operations whether the msCAn will start transmitting or go into Sleep Mode directly. During Sleep Mode the SLPAK flag is set. The application software should use this flag as a handshake indication for the request to go into Sleep mode.When in sleep mode the msCAN08 stops its own clocks and the TxCAN pin will stay in recessive state. The msCAN08 will leave sleep mode (wake-up) when bus activity occurs or when the MCU clears the SLPRQ bit.
NOTE:
The MCU can not clear the SLPRQ bit before the msCAN08 is in Sleep Mode (SLPAK = 1).
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msCAN08 Controller (msCAN08) Low power modes
msCAN08 Running SLPRQ = 0 SLPAK = 0 MCU or msCAN08 MCU
msCAN08 Sleeping SLPRQ = 1 SLPAK = 1
Sleep Request SLPRQ = 1 SLPAK = 0
msCAN08 Figure 6. Sleep request/acknowledge cycle
Soft Reset mode
In Soft Reset mode, the msCAN08 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing, and the CAN message filter. See msCAN08 module control register (CMCR0) on page 361, for a complete description of the Soft Reset mode.
Power Down mode
The msCAN08 is in Power Down mode when the CPU is in STOP mode. When entering the Power Down mode, the msCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. It is the user's responsibility to take care that the msCAN08 is not active when Power Down mode is entered. The recommended procedure is to bring the msCAN08 into Sleep mode before the STOP instruction is executed.
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msCAN08 Controller (msCAN08)
To protect the CAN bus system from fatal consequences of violations to the above rule, the msCAN08 will drive the TxCAN pin into recessive state.
CPU WAIT mode
The msCAN08 module remains active during CPU WAIT mode. The msCAN08 will stay synchronized to the CAN bus and will generate enabled transmit, receive and error interrupts to the CPU. Any such interrupt will bring the MCU out of WAIT mode.
Programmable wake-up function
The msCAN08 can be programmed to apply a low-pass filter function to the RxCAN input line while in internal sleep mode (see control bit WUPM in msCAN08 module control register (CMCR1) on page 363). This feature can be used to protect the msCAN08 from wake-up due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
Timer link
The msCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated. As the msCAN08 receiver engine receives also the frames being sent by itself, a timer signal will also be generated after a successful transmission. The previously described timer signal can be routed into the on-chip Timer Interface Module (TIM). Under the control of the Timer Link Enable (TLNKEN) bit in the CMCR0 will this signal be connected to the Timer n Channel m input1. After Timer n has been programmed to capture rising edge events it can be used to generate 16-bit time stamps which can be stored under software control with the received message.
1. The timer channel being used for the timer link is integration dependent.
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msCAN08 Controller (msCAN08) Clock system
Clock system
Figure 7shows the structure of the msCAN08 clock generation circuitry and its interaction with the Clock Generation Module (CGM). With this flexible clocking scheme the msCAN08 is able to handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
OSC
CGMXCLK
/2 CGMOUT (to SIM) BCS
PLL CGM MSCAN08
/2
(2 * Bus Freq.) /2 MSCANCLK CLKSRC Prescaler (1 .. 64) time quanta clock
Figure 7. Clocking scheme The Clock Source Flag (CLKSRC) in the msCAN08 Module Control Register (CMCR1) (see msCAN08 module control register (CMCR1) on page 363) defines whether the msCAN08 is connected to the output of the crystal oscillator or to the PLL output. A programmable prescaler is used to generate from the msCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the msCAN08. A bit time is subdivided into three segments1:
1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section 10.3.
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msCAN08 Controller (msCAN08)
* * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. Time segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
*
The Synchronization Jump Width can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. Above parameters can be set by programming the Bus Timing Registers CBTR0-1 (see msCAN08 bus timing register 0 (CBTR0) on page 364 and msCAN08 bus timing register 1 (CBTR1) on page 365). It is the user's responsibility to make sure that his bit time settings are in compliance with the CAN standard. Figure 8 and Table 3 give an overview on the CAN conforming segment settings and the related parameter values.
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msCAN08 Controller (msCAN08) Clock system
NRZ Signal
SYNC _SEG 1
Time Segment 1
(PROP_SEG + PHASE_SEG1)
Time Seg. 2
(PHASE_SEG2)
4 ... 16 8... 25 Time Quanta = 1 Bit Time
2 ... 8
Transmit Point
Sample Point (single or triple sampling)
Figure 8. Segments within the bit time Table 3. CAN standard compliant bit time segment settings
Time Segment 1
5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16
TSEG1
4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15
Time Segment 2
2 3 4 5 6 7 8
TSEG2
1 2 3 4 5 6 7
Synchron. Jump Width
1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4
SJW
0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
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msCAN08 Controller (msCAN08)
Memory map
The msCAN08 occupies 128 Byte in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128. The background receive buffer can only be read in test mode.
$xx00 $xx08 $xx09 $xx0D $xx0E $xx0F $xx10 $xx17 $xx18 $xx3F $xx40 $xx4F $xx50 $xx5F $xx60 $xx6F $xx70 $xx7F
CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES RECEIVE BUFFER TRANSMIT BUFFER 0 TRANSMIT BUFFER 1 TRANSMIT BUFFER 2
Figure 9. MSCAN08 memory map
MC68HC08AZ32 354 msCAN08 Controller (msCAN08)
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msCAN08 Controller (msCAN08) Programmer's model of message storage
ProgrammerOs model of message storage
The following section details the organisation of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification the receive and transmit message buffers have the same outline. Each message buffer allocates 16 byte in the memory map containing a 13 byte data structure. An additional Transmit Buffer Priority Register (TBPR) is defined for the transmit buffers.
Addr
xxb0 xxb1 xxb2 xxb3 xxb4 xxb5 xxb6 xxb7 xxb8 xxb9 xxbA xxbB xxbC xxbD xxbE xxbF
Register Name
Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register(1) unused unused
Figure 10. Message Buffer organisation
1. Not Applicable for Receive Buffers
Message Buffer outline
Figure 11 shows the common 13 byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12. All bits of the 13 byte data structure are undefined out of reset.
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msCAN08 Controller (msCAN08)
Identifier registers (IDRn) The identifiers consist of either 11 bits (ID10-ID0) for the standard, or 29 bits (ID28-ID0) for the extended format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
ADDR
$xxb0 $xxb1 $xxb2 $xxb3 $xxb4 $xxb5 $xxb6 $xxb7 $xxb8 $xxb9 $xxbA $xxbB $xxbC
REGISTER
IDR0 IDR1 IDR2 IDR3 DSR0 DSR1 DSR2 DSR3 DSR4 DSR5 DSR6 DSR7 DLR
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W
BIT 7
ID28 ID20 ID14 ID6 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7
BIT 6
ID27 ID19 ID13 ID5 DB6 DB6 DB6 DB6 DB6 DB6 DB6 DB6
BIT 5
ID26 ID18 ID12 ID4 DB5 DB5 DB5 DB5 DB5 DB5 DB5 DB5
BIT 4
ID25 SRR (1) ID11 ID3 DB4 DB4 DB4 DB4 DB4 DB4 DB4 DB4
BIT 3
ID24 IDE (1) ID10 ID2 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DB3 DLC3
BIT 2
ID23 ID17 ID9 ID1 DB2 DB2 DB2 DB2 DB2 DB2 DB2 DB2 DLC2
BIT 1
ID22 ID16 ID8 ID0 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1 DLC1
BIT 0
ID21 ID15 ID7 RTR DB0 DB0 DB0 DB0 DB0 DB0 DB0 DB0 DLC0
Figure 11. Receive/Transmit Message Buffer extended identifier
MC68HC08AZ32 356 msCAN08 Controller (msCAN08)
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msCAN08 Controller (msCAN08) Programmer's model of message storage
SRR -- Substitute Remote Request This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and will be stored as received on the CAN bus for receive buffers. IDE -- ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer. In case of a receive buffer the flag is set as being received and indicates to the CPU how to process the buffer identifier registers. In case of a transmit buffer the flag indicates to the msCAN08 what type of identifier to send. 1 = Extended format (29 bit) 0 = Standard format (11 bit) RTR -- Remote transmission request This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In case of a receive buffer it indicates the status of the received frame and allows to support the transmission of an answering frame in software. In case of a transmit buffer this flag defines the setting of the RTR bit to be sent. 1 = Remote frame 0 = Data frame
ADDR
$xxb0 $xxb1 $xxb2 $xxb3
REGISTER
IDR0 IDR1 IDR2 IDR3
R/W
R W R W R W R W
BIT 7
ID10 ID2
BIT 6
ID9 ID1
BIT 5
ID8 ID0
BIT 4
ID7 RTR
BIT 3
ID6 IDE(0)
BIT 2
ID5
BIT 1
ID4
BIT 0
ID3
Figure 12. Standard identifier mapping registers
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msCAN08 Controller (msCAN08)
Data length register (DLR) This register keeps the data length field of the CAN frame. DLC3-DLC0 -- Data length code bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 4 shows the effect of setting the DLC bits.
Table 4. Data length codes
Data length code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data byte count 0 1 2 3 4 5 6 7 8
Data segment registers (DSRn)
The eight data segment registers contain the data to be transmitted or being received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR.
MC68HC08AZ32 358 msCAN08 Controller (msCAN08)
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msCAN08 Controller (msCAN08) Programmer's model of message storage
Transmit buffer priority registers (TBPR)
BIT 7 TBPR $xxbD R W RESET PRIO7 U BIT 6 PRIO5 U BIT 5 PRIO5 U BIT 4 PRIO4 U BIT 3 PRIO3 U BIT 2 PRIO2 U BIT 1 PRIO1 U BIT 0 PRIO0 U
Figure 13.Transmit buffer priority register (TBPR) PRIO7-PRIO0-- Local priority This field defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the msCAN08 and is defined to be highest for the smallest binary number. The msCAN08 implements the following internal prioritization mechanism: * * * All transmission buffers with a cleared TXE flag participate in the prioritization right before the SOF (Start of Frame) is sent. The transmission buffer with the lowest local priority field wins the prioritization. In case of more than one buffer having the same lowest priority the message buffer with the lower index number wins.
CAUTION:
To ensure data integrity, no registers of the transmit buffers shall be written while the associated TXE flag is cleared. Also, no registers of the receive buffer shall be read while the RXF flag is cleared.
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MC68HC08AZ32 msCAN08 Controller (msCAN08) 359
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msCAN08 Controller (msCAN08)
ProgrammerOs model of control registers
Overview The programmer's model has been laid out for maximum simplicity and efficiency. The Figure 14 gives an overview on the control register block of the msCAN08:
REGISTER
CMCR0 CMCR1 CBTR0 CBTR1 CRFLG CRIER CTFLG CTCR CIDAC reserved CRXERR CTXERR CIDAR0 CIDAR1 CIDAR2 CIDAR3
ADDR
$xx00 $xx01 $xx02 $xx03 $xx04 $xx05 $xx06 $xx07 $xx08 $xx09-$ xx0D $xx0E $xx0F $xx10 $xx11 $xx12 $xx13
R/W
R W R W* R
W
BIT 7
0 0
BIT 6
0 0
BIT 5
0 0
BIT 4
SYNCH 0
BIT 3
TLNKEN 0
BIT 2
SLPAK
BIT 1
BIT 0
SLPRQ SFTRES WUPM CLKSRC BRP1 BRP0
LOOPB BRP2
SJW1 SAMP
SJW0
BRP5
BRP4
BRP3
R W* R W R W R W R W R W* R W R W R W R W* R W* R W* R W*
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 OVRIF OVRIE TXE1 RXF RXFIE TXE0
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 TXE2
ABTRQ2 ABTRQ1 ABTRQ0 0 IDAM1 IDAM0
TXEIE2 TXEIE1 TXEIE0 0 IDHIT1 IDHIT0
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC7 AC7 AC7 AC6 AC6 AC6 AC6 AC5 AC5 AC5 AC5 AC4 AC4 AC4 AC4 AC3 AC3 AC3 AC3 AC2 AC2 AC2 AC2 AC1 AC1 AC1 AC1 AC0 AC0 AC0 AC0
= Unimplemented
Figure 14. MSCAN08 Control Register Structure
MC68HC08AZ32 360 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
ADDR
$xx14 $xx15 $xx16 $xx17
REGISTER
CIDMR0 CIDMR1 CIDMR2 CIDMR3
R/W
R W* R W* R W* R W*
BIT 7
AM7 AM7 AM7 AM7
BIT 6
AM6 AM6 AM6 AM6
BIT 5
AM5 AM5 AM5 AM5
BIT 4
AM4 AM4 AM4 AM4
BIT 3
AM3 AM3 AM3 AM3
BIT 2
AM2 AM2 AM2 AM2
BIT 1
AM1 AM1 AM1 AM1
BIT 0
AM0 AM0 AM0 AM0
= Unimplemented
Figure 14. MSCAN08 Control Register Structure (Continued)
msCAN08 module control register (CMCR0)
.
BIT 7 CMCR0 $xx00 R W RESET 0 0
BIT 6 0 0
BIT 5 0 0
BIT 4 SYNCH 0
BIT 3 TLNKEN 0
BIT 2 SLPAK 0
BIT 1 SLPRQ 0
BIT 0 SFTRES 1
= Unimplemented
Figure 15. Module control register 0 (CMCR0) SYNCH -- Synchronized status This bit indicates whether the msCAN08 is synchronized to the CAN bus and as such can participate in the communication process. 1 = msCAN08 is synchronized to the CAN bus 0 = msCAN08 is not synchronized to the CAN bus TLNKEN -- Timer enable This flag is used to establish a link between the msCAN08 and the on-chip timer (see Timer link on page 350). 1 = The msCAN08 timer signal output is connected to the timer. 0 = No connection.
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msCAN08 Controller (msCAN08)
SLPAK -- Sleep mode acknowledge This flag indicates whether the msCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see msCAN08 internal sleep mode on page 348). 1 = Sleep - The msCAN08 is in internal sleep mode. 0 = Wake-up - The msCAN08 will function normally. SLPRQ -- Sleep request, go to internal sleep mode This flag allows to request the msCAN08 to go into an internal power-saving mode (see msCAN08 internal sleep mode on page 348). 1 = Sleep - The msCAN08 will go into internal sleep mode if and as long as there is no activity on the bus. 0 = Wake-up - The msCAN08 will function normally. If SLPRQ is cleared by the CPU then the msCAN08 will wake up, but will not issue a wake-up interrupt. SFTRES -- Soft reset When this bit is set by the CPU, the msCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers will go into the same state as out of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR. The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0-3, CIDMR0-3 can only be written by the CPU when the msCAN08 is in soft reset state. The values of the error counters are not affected by soft reset. When this bit is cleared by the CPU, the msCAN08 will try to synchronize to the CAN bus: If the msCAN08 is not in bus-off state it will be synchronized after 11 recessive bits on the bus; if the msCAN08 is in bus-off state it continues to wait for 128 occurrences of 11 recessive bits. 1 = msCAN08 in soft reset state. 0 = Normal operation
MC68HC08AZ32 362 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
msCAN08 module control register (CMCR1)
.
BIT 7 CMCR1 $xx01 R W RESET 0 0
BIT 6 0 0
BIT 5 0 0
BIT 4 0 0
BIT 3 0 0
BIT 2 LOOPB 0
BIT 1 WUPM 0
BIT 0 CLKSRC 0
= Unimplemented
Figure 16. Module control register 1 (CMCR1) LOOPB -- Loop back self test mode When this bit is set the msCAN08 performs an internal loop back which can be used for self test operation: the bit stream output of the transmitter is fed back to the receiver. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (1). Note that in this state the msCAN08 ignores the ACK bit to insure proper reception of its own message and will treat messages being received while in transmission as received messages from remote nodes. 1 = Activate loop back self test mode 0 = Normal operation WUPM -- Wake-up mode This flag defines whether the integrated low-pass filter is applied to protect the msCAN08 from spurious wake-ups (see Programmable wake-up function on page 350). 1 = msCAN08 will wake up the CPU only in case of dominant pulse on the bus which has a length of at least approximately Twup. 0 = msCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus. CLKSRC -- Clock source This flag defines which clock source the msCAN08 module is driven from (see Clock system on page 351). 1 = THE msCAN08 clock source is CGMOUT (see Figure 7). 0 = The msCAN08 clock source is CGMXCLK/2 (see Figure 7).
NOTE:
The CMCR1 register can only be written if the SFTRES bit in the msCAN08 Module Control Register is set
MC68HC08AZ32 msCAN08 Controller (msCAN08) 363
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msCAN08 Controller (msCAN08)
msCAN08 bus timing register 0 (CBTR0)
BIT 7 CBTR0 $xx02 R W RESET SJW1 0 BIT 6 SJW0 0 BIT 5 BRP5 0 BIT 4 BRP4 0 BIT 3 BRP3 0 BIT 2 BRP2 0 BIT 1 BRP1 0 BIT 0 BRP0 0
Figure 17. Bus timing register 0 SJW1, SJW0 -- Synchronization jump width The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 5). Table 5. Synchronization jump width
SJW1
0 0 1 1
SJW0
0 1 0 1
Synchronization jump width
1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles
BRP5-BRP0 -- Baud Rate Prescaler These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing, according to Table 6.
Table 6. Baud rate prescaler
BRP5 0 0 0 0 : : 1 MC68HC08AZ32 364 msCAN08 Controller (msCAN08) BRP4 0 0 0 0 : : 1 BRP3 0 0 0 0 : : 1 BRP2 0 0 0 0 : : 1 BRP1 0 0 1 1 : : 1 BRP0 0 1 0 1 : : 1 Prescaler value (P) 1 2 3 4 : : 64
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
NOTE:
The CBTR0 register can only be written if the SFTRES bit in the MSCAN08 Module Control Register is set.
msCAN08 bus timing register 1 (CBTR1)
.
BIT 7 CBTR1 $xx03 R W RESET SAMP 0
BIT 6 TSEG22 0
BIT 5 TSEG21 0
BIT 4 TSEG20 0
BIT 3 TSEG13 0
BIT 2 TSEG12 0
BIT 1 TSEG11 0
BIT 0 TSEG10 0
Figure 18. Bus timing register 1 SAMP -- Sampling This bit determines the number of samples of the serial bus to be taken per bit time. If set three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For higher bit rates SAMP should be cleared, which means that only one sample will be taken per bit. 1 = Three samples per bit. 0 = One sample per bit. TSEG22-TSEG10 -- Time segment Time segments within the bit time fix the number of clock cycles per bit time, and the location of the sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 8. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown above).
NOTE:
The CBTR1 register can only be written if the SFTRES bit in the msCAN08 Module Control Register is set.
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msCAN08 Controller (msCAN08)
Table 7. Time segment syntax
SYNC_SEG Transmit point System expects transitions to occur on the bus during this period. A node in transmit mode will transfer a new value to the CAN bus at this point. A node in receive mode will sample the bus at this point. If the three samples per bit option is selected then this point marks the position of the third sample.
Sample point
.
Table 8. Time segment values
TSEG TSEG TSEG TSEG 13 12 11 10
0 0 0 0 . . 1 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1
Time segment 1
1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles . . 16 Tq clock cycles
TSEG TSEG TSEG 22 21 20
0 0 . . 1 0 0 . . 1 0 1 . . 1
Time segment 2
1 Tq clock cycle 2 Tq clock cycles . . 8 Tq clock cycles
msCAN08 receiver flag register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can only be cleared when the condition which caused the setting is no more valid. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.
BIT 7 BIT 6 RWRNIF 0 BIT 5 TWRNIF 0 BIT 4 RERRIF 0 BIT 3 TERRIF 0 BIT 2 BOFFIF 0 BIT 1 OVRIF 0 BIT 0 RXF 0
CRFLG $xx04
R W
WUPIF 0
RESET
Figure 19. Receiver flag register
MC68HC08AZ32 366 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
WUPIF -- Wake-up interrupt flag If the msCAN08 detects bus activity whilst it is asleep, it clears the SLPAK bit in the CMCR0 register; the WUPIF bit will then be set. If not masked, a Wake-Up interrupt is pending while this flag is set. 1 = msCAN08 has detected activity on the bus and requested wake-up. 0 = No wake-up activity has been observed while in sleep mode. RWRNIF -- Receiver warning interrupt flag This bit will be set when the msCAN08 went into warning status due to the Receive Error counter being in the range of 96 to 127. If not masked, an Error interrupt is pending while this flag is set. 1 = msCAN08 went into receiver warning status. 0 = No receiver warning status has been reached. TWRNIF -- Transmitter warning interrupt flag This bit will be set when the msCAN08 went into warning status due to the Transmit Error counter being in the range of 96 to 127. If not masked, an Error interrupt is pending while this flag is set. 1 = msCAN08 went into transmitter warning status. 0 = No transmitter warning status has been reached. RERRIF -- Receiver error Passive Interrupt Flag This bit will be set when the msCAN08 went into error passive status due to the Receive Error counter exceeded 127. If not masked, an Error interrupt is pending while this flag is set. 1 = msCAN08 went into receiver error passive status. 0 = No receiver error passive status has been reached. TERRIF -- Transmitter Error Passive Interrupt Flag This bit will be set when the msCAN08 went into error passive status due to the Transmit Error counter exceeded 127. If not masked, an Error interrupt is pending while this flag is set. 1 = msCAN08 went into transmitter error passive status. 0 = No transmitter error passive status has been reached.
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MC68HC08AZ32 msCAN08 Controller (msCAN08) 367
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msCAN08 Controller (msCAN08)
BOFFIF -- Bus-Off Interrupt Flag This bit will be set when the msCAN08 went into bus-off status, due to the Transmit Error counter exceeded 255. If not masked, an Error interrupt is pending while this flag is set. 1 = msCAN08 went into bus-off status. 0 = No bus-off status has been reached. OVRIF -- Overrun Interrupt Flag This bit will be set when a data overrun condition occurred. If not masked, an Error interrupt is pending while this flag is set. 1 = A data overrun has been detected. 0 = No data overrun has occurred. RXF -- Receive Buffer Full The RXF flag is set by the msCAN08 when a new message is available in the foreground receive buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the CPU has read that message from the receive buffer the RXF flag must be handshaken to release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. In that case the msCAN08 will signal an overload condition. If not masked, a Receive interrupt is pending while this flag is set. 1 = The receive buffer is full. A new message is available. 0 = The receive buffer is released (not full).
NOTE:
The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
MC68HC08AZ32 368 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
msCAN08 Receiver Interrupt Enable Register (CRIER)
BIT 7 CRIER $xx05 R W RESET WUPIE 0 BIT 6 RWRNIE 0 BIT 5 TWRNIE 0 BIT 4 RERRIE 0 BIT 3 TERRIE 0 BIT 2 BOFFIE 0 BIT 1 OVRIE 0 BIT 0 RXFIE 0
Figure 20. Receiver Interrupt Enable Register WUPIE -- Wake-up Interrupt Enable 1 = A wake-up event will result in a wake-up interrupt. 0 = No interrupt will be generated from this event. RWRNIE -- Receiver Warning Interrupt Enable 1 = A receiver warning status event will result in an error interrupt. 0 = No interrupt will be generated from this event. TWRNIE -- Transmitter Warning Interrupt Enable 1 = A transmitter warning status event will result in an error interrupt. 0 = No interrupt will be generated from this event. RERRIE -- Receiver Error Passive Interrupt Enable 1 = A receiver error passive status event will result in an error interrupt. 0 = No interrupt will be generated from this event. TERRIE -- Transmitter Error Passive Interrupt Enable 1 = A transmitter error passive status event will result in an error interrupt. 0 = No interrupt will be generated from this event. BOFFIE -- Bus-Off Interrupt Enable 1 = A bus-off event will result in an error interrupt. 0 = No interrupt will be generated from this event. OVRIE -- Overrun Interrupt Enable 1 = An overrun event will result in an error interrupt. 0 = No interrupt will be generated from this event.
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msCAN08 Controller (msCAN08)
RXFIE -- Receiver Full Interrupt Enable 1 = A receive buffer full (successful message reception) event will result in a receive interrupt. 0 = No interrupt will be generated from this event.
NOTE:
The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set.
msCAN08 Transmitter Flag Register (CTFLG)
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CTCR register. A hard or soft reset will clear the register.
BIT 7 BIT 6 ABTAK2 0 BIT 5 ABTAK1 0 BIT 4 ABTAK0 0 BIT 3 0 0 BIT 2 TXE2 1 BIT 1 TXE1 1 BIT 0 TXE0 1
CTFLG $xx06
R W
0 0
RESET
= Unimplemented
Figure 21. Transmitter Flag Register
ABTAK2-ABTAK0 -- Abort Acknowledge This flag acknowledges that a message has been aborted due to a pending abort request from the CPU. After a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent in the meantime. The flag is reset implicitly whenever the associated TXE flag is set to 0. 1 = The message has been aborted. 0 = The massage has not been aborted, thus has been sent out. TXE2-TXE0 --Transmitter Buffer Empty This flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. The CPU must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. The msCAN08 will set the flag after the message has been sent successfully. The flag will also be set by the msCAN08 when the transmission request was
MC68HC08AZ32 370 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
successfully aborted due to a pending abort request (see msCAN08 Transmitter Control Register (CTCR) on page 371). If not masked, a Transmit interrupt is pending while this flag is set. A reset of this flag will also reset the Abort Acknowledge (ABTAK, see above) and the Abort Request (ABTRQ) (see msCAN08 Transmitter Control Register (CTCR) on page 371), flags of the particular buffer. 1 = The associated message buffer is empty (not scheduled). 0 = The associated message buffer is full (loaded with a message due for transmission).
NOTE:
The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
msCAN08 Transmitter Control Register (CTCR)
BIT 7 CTCR $xx07 R W RESET 0 0 BIT 6 ABTRQ2 0 BIT 5 ABTRQ1 0 BIT 4 ABTRQ0 0 BIT 3 0 0 BIT 2 TXEIE2 0 BIT 1 TXEIE1 0 BIT 0 TXEIE0 0
= Unimplemented
Table 9. Transmitter Control Register
ABTRQ2-ABTRQ0 -- Abort Request The CPU sets this bit to request that an already scheduled message buffer (TXE = 0) shall be aborted. The msCAN08 will grant the request when the message is not already under transmission. When a message is aborted the associated TXE and the Abort Acknowledge flag ABTAK) (see msCAN08 Transmitter Flag Register (CTFLG) on page 370), will be set and an TXE interrupt will occur if enabled. The CPU can not reset ABTRQx. ABTRQx is reset implicitly whenever the associated TXE flag is set. 1 = Abort request pending. 0 = No abort request.
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MC68HC08AZ32 msCAN08 Controller (msCAN08) 371
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msCAN08 Controller (msCAN08)
TXEIE2-TXEIE0 -- Transmitter Empty Interrupt Enable 1 = A transmitter empty (transmit buffer available for transmission) event will result in a transmitter empty interrupt. 0 = No interrupt will be generated from this event.
NOTE:
The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set.
msCAN08 Identifier Acceptance Control Register (CIDAC)
BIT 7 CIDAC $xx08 R W RESET 0 0 0 BIT 6 0 BIT 5 IDAM1 0 BIT 4 IDAM0 0 BIT 3 0 0 BIT 2 0 0 BIT 1 IDHIT1 0 BIT 0 IDHIT0 0
= Unimplemented
Figure 22. Identifier Acceptance Control Register IDAM1-IDAM0-- Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see Identifier acceptance filter on page 340). Table 10 summarizes the different settings. In "Filter Closed" mode no messages will be accepted such that the foreground buffer will never be reloaded.
Table 10. Identifier Acceptance Mode Settings
IDAM1
0 0 1 1
IDAM0
0 1 0 1
Identifier Acceptance Mode
Single 32 bit Acceptance Filter Two 16 bit Acceptance Filter Four 8 bit Acceptance Filters Filter Closed
MC68HC08AZ32 372 msCAN08 Controller (msCAN08)
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MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
IDHIT1-IDHIT0-- Identifier Acceptance Hit Indicator The msCAN08 sets these flags to indicate an identifier acceptance hit (see Identifier acceptance filter on page 340). Table 11 summarizes the different settings.
Table 11. Identifier Acceptance Hit Indication
IDHIT1
0 0 1 1
IDHIT0
0 1 0 1
Identifier Acceptance Hit
Filter 0 Hit Filter 1 Hit Filter 2 Hit Filter 3 Hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets copied from the background to the foreground buffer the indicators are updated as well.
NOTE:
The CIDAC register can only be written if the SFTRES bit in the msCAN08 Module Control Register is set.
msCAN08 Receive Error Counter (CRXERR)
BIT 7 CRXERR $xx0E R RXERR7 W RESET 0 0 0 0 0 0 0 0 = Unimplemented BIT 6 RXERR6 BIT 5 RXERR5 BIT 4 RXERR4 BIT 3 RXERR3 BIT 2 RXERR2 BIT 1 RXERR1 BIT 0 RXERR0
Figure 23. Receive Error Counter This register reflects the status of the msCAN08 receive error counter. The register is read only.
43-can
MC68HC08AZ32 msCAN08 Controller (msCAN08) 373
MOTOROLA
msCAN08 Controller (msCAN08)
msCAN08 Transmit Error Counter (CTXERR)
BIT 7 CTXERR $xx0F R TXERR7 W RESET 0 0 0 0 0 0 0 0 = Unimplemented BIT 6 TXERR6 BIT 5 TXERR5 BIT 4 TXERR4 BIT 3 TXERR3 BIT 2 TXERR2 BIT 1 TXERR1 BIT 0 TXERR0
Figure 24. Transmit Error Counter This register reflects the status of the msCAN08 transmit error counter. The register is read only.
NOTE:
Both error counters may only be read when in Sleep or SOft Reset Mode.
msCAN08 Identifier Acceptance Registers (CIDAR0-3)
On reception each message is written into the background receive buffer. The CPU is only signalled to read the message however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). The acceptance registers of the msCAN08 are applied on the IDR0 to IDR3 registers of incoming messages in a bit by bit manner. For extended identifiers all four acceptance and mask registers are applied. For standard identifiers only the first two (IDAR0, IDAR1) are applied. In the latter case it is required to program the mask register CIDMR1 in the three last bits (AC2 - AC0) to `don't care'.
MC68HC08AZ32 374 msCAN08 Controller (msCAN08)
44-can
MOTOROLA
msCAN08 Controller (msCAN08) Programmer's model of control registers
BIT 7 CIDAR0 $xx10 CIDAR1 $xx11 CIDAR2 $xx12 CIDAR3 $xx13 R W R W R W R W RESET AC7 AC7 AC7 AC7 U
BIT 6 AC6 AC6 AC6 AC6 U U
BIT 5 AC5 AC5 AC5 AC5 U = Unaffected
BIT 4 AC4 AC4 AC4 AC4 U
BIT 3 AC3 AC3 AC3 AC3 U
BIT 2 AC2 AC2 AC2 AC2 U
BIT 1 AC1 AC1 AC1 AC1 U
BIT 0 AC0 AC0 AC0 AC0 U
Figure 25. Identifier Acceptance Registers AC7-AC0 -- Acceptance Code Bits AC7-AC0 comprise a user defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
NOTE:
The CIDAR0-3 registers can only be written if the SFTRES bit in the msCAN08 Module Control Register is set
msCAN08 Identifier Mask Registers (CIDMR0-3)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering.
BIT 7 CIDMR0 $xx14 CIDMR1 $xx15 CIDMR2 $xx16 CIDMR3 $xx17 R W R W R W R W RESET AM7 AM7 AM7 AM7 U
BIT 6 AM6 AM6 AM6 AM6 U U
BIT 5 AM5 AM5 AM5 AM5 U = Unaffected
BIT 4 AM4 AM4 AM4 AM4 U
BIT 3 AM3 AM3 AM3 AM3 U
BIT 2 AM2 AM2 AM2 AM2 U
BIT 1 AM1 AM1 AM1 AM1 U
BIT 0 AM0 AM0 AM0 AM0 U
Figure 26. Identifier Mask Registers
45-can
MC68HC08AZ32 msCAN08 Controller (msCAN08) 375
MOTOROLA
msCAN08 Controller (msCAN08)
AM7-AM0 -- Acceptance Mask Bits If a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit, before a match will be detected. The message will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted. Bit description: 1 = Ignore corresponding acceptance code register bit. 0 = Match corresponding acceptance code register and identifier bits.
NOTE:
The CIDMR0-3 registers can only be written if the SFTRES bit in the msCAN08 Module Control Register is set
MC68HC08AZ32 376 msCAN08 Controller (msCAN08)
46-can
MOTOROLA
Specifications Specifications
Contents
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 380 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 5.0 vdc 0.5v Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 383 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 CGM Acquisition/Lock Time Information. . . . . . . . . . . . . . . . . . . . . . 387 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 64-pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
1-specs
MC68HC08AZ32 Specifications 377
MOTOROLA
Specications
Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate at the maximum ratings. Refer to 5.0 Volt DC Electrical Characteristics on page 380 for guaranteed operating conditions.
Rating Supply Voltage Input Voltage Maximum Current Per Pin Excluding VDD and VSS Storage Temperature Maximum Current out of VSS Maximum Current into VDD Reset IRQ Input Voltage NOTE: Voltages are referenced to VSS. Symbol VDD VIN I TSTG IMVSS IMVDD VHI Value -0.3 to +6.0 VSS -0.3 to VDD +0.3 25 -55 to +150 100 100 VDD +2 to VDD + 4 Unit V V mA C mA mA V
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).
MC68HC08AZ32 378 Specifications
2-specs
MOTOROLA
Specifications Functional Operating Range
Functional Operating Range
Rating Operating Temperature Range(1) Operating Voltage Range
1. TA (MAX) = 125C for part suffix MFU 105C for part suffix VFU 85C for part suffix CFU
Symbol TA VDD
Value -40 to TA (max) 5.0 0.5v
Unit C V
NOTE:
For applications which use the LVI, Motorola guarantee the functionality of the device down to the LVI trip point (VLVII).
Thermal Characteristics
Characteristic Thermal Resistance QFP (64 Pins) I/O Pin Power Dissipation Power Dissipation (see Note 1) Constant (see Note 2) Average Junction Temperature Symbol JA PI/O PD K TJ Value 70 User Determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C PD x (TA + 273 C) + (PD2 x JA) TA = PD Unit C/W W W W/C C
x JA
NOTES: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With this value of K, PD, and TJ can be determined for any value of TA.
3-specs
MC68HC08AZ32 Specifications 379
MOTOROLA
Specications
5.0 Volt DC Electrical Characteristics
Characteristic Output High Voltage (ILOAD = -2.0 mA) All Ports (ILOAD = -5.0 mA) All Ports Total source current Output Low Voltage (ILOAD = 1.6 mA) All Ports (ILOAD = 10.0 mA) All Ports Total sink current Input High Voltage All Ports, IRQs, RESET, OSC1 Input Low Voltage All Ports, IRQs, RESET, OSC1 VDD + VDDA Supply Current Run (see Note 3)(see Note 10) Wait (see Note 4)(see Note 10) Stop (see Note 5) 25 C -40 C to +125 C 25 C with LVI Enabled -40 C to +125 C with LVI Enabled I/O Ports Hi-Z Leakage Current Input Current Capacitance Ports (As Input or Output) Low-Voltage Reset Inhibit (trip) (recover) VOL IOLtot VIH VIL -- -- -- 0.7 x VDD VSS -- -- IDD -- -- -- -- -- -- -- -- 4.0 4.4 0 0 0.02 VDD 200 800 -- VDD + 2 0.4 1.5 15 VDD 0.3 x VDD 30 14 50 100 400 500 1 1 12 8 V V mA V V VOH IOHtot VDD -0.8 VDD -1.5 -- -- -- 10 V V mA Symbol Min Max Unit
mA mA A A A A A A pF V mV mV V/ms V
IL IIN COUT CIN VLVI VPOR VPORRST RPOR VHI
POR ReArm Voltage (see Note 6) POR Reset Voltage (see Note 7) POR Rise Time Ramp Rate (see Note 8) High COP Disable Voltage (see Note 9)
MC68HC08AZ32 380 Specifications
4-specs
MOTOROLA
Specifications Control Timing
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA (MAX), unless otherwise noted. 2.Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3.Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4.Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled. 5.Stop IDD measured with OSC1 = VSS. 6.Maximum is highest voltage that POR is guaranteed. 7.Maximum is highest voltage that POR is possible. 8.If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 9.See Computer Operating Properly Module (COP) on page 143. 10.Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies.
Control Timing
Characteristic Bus Operating Frequency (4.5-5.5 V -- VDD Only) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period EEPROM Programming Time per Byte EEPROM Erasing Time per Byte EEPROM Erasing Time per Block EEPROM Erasing Time per Bulk EEPROM Programming Voltage Discharge Period 16-Bit Timer (see Note 2) Input Capture Pulse Width (see Note 3) Input Capture Period MSCAN Wake-up Filter Pulse Width (see Note 5) Symbol fBUS tRL tILHI tILIL tEEPGM tEBYTE tEBLOCK tEBULK tEEFPV tTH, tTL tTLTL tWUP Min -- 1.5 1.5 Note 3 10 10 10 10 100 2 Note 4 2 Max 8.4 -- -- -- -- -- -- -- 200 -- -- 5 Unit MHz tcyc tcyc tcyc ms ms ms ms s tcyc s
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA (MAX), unless otherwise noted. 2.The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3.Refer to Mode, edge, and level selection on page 276 and supporting note. 4.The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus TBD tcyc. 5. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
5-specs
MC68HC08AZ32 Specifications 381
MOTOROLA
Specications
ADC Characteristics
Characteristic Resolution Absolute Accuracy (VREFL = 0 V, VDDA = VREFH = 5 V 0.5v) Conversion Range (see Note 1) Power-Up Time Input Leakage (see Note 3) Ports B and D Conversion Time Monotonicity Zero Input Reading Full-Scale Reading Sample Time (see Note 2) Input Capacitance ADC Internal Clock Analog Input Voltage 00 FE 5 -- 500 k VREFL Min 8 -1 VREFL 16 -- Max 8 +1 VREFH 17 1 Unit Bits LSB V s A ADC Clock Cycles Includes Sampling Time Includes Quantization VREFL = VSSA Conversion Time Period Comments
16
17
Inherent within Total Error 01 FF -- 8 1.048 M VREFH Hex Hex ADC Clock Cycles pF Hz V Not Tested Tested Only at 1 MHz VIN = VREFL VIN = VREFH
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc 0.5v, VSSA = 0 Vdc, VREFH = 5.0 Vdc 0.5v 2.Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3.The external system error caused by input leakage current is approximately equal to the product of R source and input current.
MC68HC08AZ32 382 Specifications
6-specs
MOTOROLA
Specifications 5.0 vdc 0.5v Serial Peripheral Interface (SPI) Timing
5.0 vdc 0.5v Serial Peripheral Interface (SPI) Timing
Num Characteristic Operating Frequency (see Note 3) Master Slave 1 2 3 4 Cycle Time Master Slave Enable Lead Time Enable Lag Time Clock (SCK) High Time Master Slave Clock (SCK) Low Time Master Slave Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Access Time, Slave (see Note 4) CPHA = 0 CPHA = 1 Slave Disable Time (Hold Time to High-Impedance State) (see Note 5) Data Valid Time after Enable Edge (see Note 6) Master Slave Data Hold Time (Outputs, after Enable Edge) Master Slave Symbol fBUS(M) fBUS(S) tcyc(M) tcyc(S) tLead tLag tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS Min fBUS/128 dc 2 1 15 15 100 50 100 50 45 5 0 15 0 0 -- Max fBUS/2 fBUS 128 -- -- -- -- -- -- -- -- -- -- -- 40 20 25 Unit MHz
tcyc ns ns ns
5
ns
6
ns
7
ns
8 9
ns
ns
10
tV(M) tV(S) tHO(M) tHO(S)
-- -- 0 5
10 40 -- --
ns
11
1. 2. 3. 4. 5. 6.
ns
All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins. Item numbers refer to dimensions in Figure 1 and Figure 2. fBUS = the currently active bus frequency for the microcontroller. Time to data active from high-impedance state. Hold time to high-impedance state. With 100 pF on all SPI pins
7-specs
MC68HC08AZ32 Specifications 383
MOTOROLA
Specications
SS INPUT
SS PIN OF MASTER HELD HIGH 1 12 5 4 12 13 13 12
SCK (CPOL = 0) OUTPUT NOTE
SCK (CPOL = 1) OUTPUT NOTE
5 4 6 7 LSB IN 10 BIT 6-1 11 (REF) MASTER LSB OUT 12
MISO INPUT 10 (REF) MOSI OUTPUT 13
MSB IN 11 MASTER MSB OUT
BIT 6-1
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS INPUT
SS PIN OF MASTER HELD HIGH 1 13 5 4 12 13 NOTE 6 7 LSB IN 10 BIT 6-1 11 MASTER LSB OUT 12 12 NOTE
SCK (CPOL = 0) OUTPUT
SCK (CPOL = 1) OUTPUT
5 4
MISO INPUT 10 (REF) MOSI OUTPUT 13
MSB IN 11 MASTER MSB OUT
BIT 6-1
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1) Figure 1. SPI Master Timing Diagram
MC68HC08AZ32 384 Specifications
8-specs
MOTOROLA
Specifications 5.0 vdc 0.5v Serial Peripheral Interface (SPI) Timing
SS INPUT 1 SCK (CPOL = 0) INPUT 2 SCK (CPOL = 1) INPUT 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT MSB IN 7 10 BIT 6-1 BIT 6-1 11 5 4 12 13 SLAVE LSB OUT 11 LSB IN 9 NOTE 5 4 13 12 3
NOTE: Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS INPUT 1 SCK (CPOL = 0) INPUT 2 SCK (CPOL = 1) INPUT 8 MISO OUTPUT 5 4 10 NOTE SLAVE MSB OUT 6 MOSI INPUT 7 MSB IN 10 BIT 6-1 12 BIT 6-1 11 LSB IN 13 9 SLAVE LSB OUT 5 4 3 13 12
NOTE: Not defined but normally LSB of character previously transmitted.
a) SPI Slave Timing (CPHA = 1) Figure 2. SPI Slave Timing Diagram
9-specs
MC68HC08AZ32 Specifications 385
MOTOROLA
Specications
CGM Operating Conditions
Characteristic Operating Voltage Crystal Reference Frequency Module Crystal Reference Frequency Range Nom. Multiplier (MHz) VCO Center-of-Range Frequency (MHz) VCO Operating Frequency (MHZ) Symbol VDD fRCLK fXCLK fNOM fVRS fVCLK Min 4.5 V 1 -- -- 4.9152 4.9152 Typ -- 4.9152 MHz 4.9152 MHz 4.9152 -- -- Max 5.5 V 8 -- -- 32.0 32.0 Same Frequency as fRCLK 4.5-5.5 V, VDD only 4.5-5.5 V, VDD only Comments
CGM Component Information
Description Crystal Load Capacitance Crystal Fixed Capacitance Crystal Tuning Capacitance Filter Capacitor Multiply Factor Symbol CL C1 C2 CFACT Min -- -- -- Typ -- 2 x CL 2 x CL 0.0154 CFACT x (VDDA/ fXCLK) Max -- -- -- Comments Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data F/s V See External filter --
capacitor pin (CGMXFC) on page 102.
Filter Capacitor
CF
--
Bypass Capacitor
CBYP
--
0.1 F
--
CBYP must provide low AC impedance from f = fXCLK/100 to 100 x fVCLK, so series resistance must be considered.
MC68HC08AZ32 386 Specifications
10-specs
MOTOROLA
Specifications CGM Acquisition/Lock Time Information
CGM Acquisition/Lock Time Information
Description Manual Mode Time to Stable Manual Stable to Lock Time Manual Acquisition Time Tracking Mode Entry Frequency Tolerance Acquisition Mode Entry Frequency Tolerance LOCK Entry Freq. Tolerance LOCK Exit Freq. Tolerance Reference Cycles per Acquisition Mode Measurement Reference Cycles per Tracking Mode Measurement Automatic Mode Time to Stable Automatic Stable to Lock Time Automatic Lock Time PLL Jitter, Deviation of Average Bus Frequency over 2 ms 1.GBNT guaranteed but not tested
2.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA (MAX), unless otherwise noted.
Symbol tACQ tAL tLOCK DTRK DUNT DLOCK DUNL nACQ
Min -- -- -- 0 6.3% 0 0.9% --
Typ (8 x VDDA)/(fXCLK x KACQ) (4 x VDDA)/(fXCLK x KTRK) tACQ+tAL -- -- -- -- 32
Max -- -- -- 3.6% 7.2% 0.9% 1.8% --
Notes If CF Chosen Correctly If CF Chosen Correctly
nTRK
--
128
-- If CF Chosen Correctly -- -- (fCRYS) x (.025%) x (N/4) N = VCO Freq. Mult. (GBNT) If CF Chosen Correctly
tACQ tAL tLOCK
nACQ/fXCLK nTRK/fXCLK -- 0
(8 x VDDA)/(fXCLK x KACQ) (4 x VDDA)/(fXCLK x KTRK) tACQ+tAL --
11-specs
MC68HC08AZ32 Specifications 387
MOTOROLA
Specications
Timer Module Characteristics
Characteristic Input Capture Pulse Width Input Clock Pulse Width Symbol tTIH, tTIL tTCH, tTCL Min 125 (1/fOP) + 5 Max -- -- Unit ns ns
Memory Characteristics
Characteristic RAM Data Retention Voltage EEPROM Programming Time per Byte EEPROM Erasing Time per Byte EEPROM Erasing Time per Block EEPROM Erasing Time per Bulk EEPROM Programming Voltage Discharge Period EEPROM Write/Erase Cycles @ 10 ms Write Time +125 C EEPROM Data Retention After 10,000 Write/Erase Cycles EEPROM enable recovery time EEPROM stop recovery time tEEOFF tEESTOP Symbol VRDR tEEPGM tEEBYTE tEEBLOCK tEEBULK tEEFPV Min 0.7 10 10 10 10 100 10,000 10 600 600 Max -- -- -- -- -- -- -- -- -- -- Unit V ms ms ms ms s Cycles Years s s
MC68HC08AZ32 388 Specifications
12-specs
MOTOROLA
Specifications Mechanical Specifications
Mechanical Specifications
64-pin Quad Flat Pack (QFP)
L
48 49 33 32 S S
D
S
S
D
B B P
0.20 (0.008) M C A-B 0.05 (0.002) A-B
-AL
-BB
V
0.20 (0.008)
M
H A-B
-A-, -B-, DDETAIL A
DETAIL A
64
17
1
16
F
-DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B 0.20 (0.008) E C -CSEATING PLANE M S
D
S
J
N
S H A-B
S
D
S BASE METAL
M
DETAIL C 0.20 (0.008) -HDATUM PLANE
D
M
C A-B
S
D
S
SECTION B-B
H
G
M
0.01 (0.004)
U T R
DATUM PLANE
-HQ K W X DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.45 2.15 0.45 0.30 2.40 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 12.00 REF 10 5 0.17 0.13 0.40 BSC 7 0 0.30 0.13 16.95 17.45 0.13 0 16.95 17.45 0.45 0.35 1.6 REF
INCHES MIN MAX 0.547 0.555 0.547 0.555 0.085 0.096 0.012 0.018 0.079 0.094 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.472 REF 5 10 0.005 0.007 0.016 BSC 0 7 0.005 0.012 0.667 0.687 0.005 0 0.667 0.687 0.014 0.018 0.063 REF
Figure 3. 64-pin QFP (case #840C)
13-specs
MC68HC08AZ32 Specifications 389
MOTOROLA
Specications
MC68HC08AZ32 390 Specifications
14-specs
MOTOROLA
Appendix A: Future EEPROM Registers Appendix A: Future EEPROM Registers
NOTE:
The following are proposed register addresses. Writing to them in current software will have no effect.
EEPROM Timebase Divider Control Registers
To program or erase the EEPROM content, the EEPROM control hardware requires a constant timebase of 35s to drive its internal timer. EEPROM Timebase Divider EEDIV is a clock-divider which divides the selected reference clock source to generate this constant timebase. The reference clock input of the EEDIV is driven by either the CGMXCLK or the system bus clock. The selection of this reference clock is defined by the EEDIVCLK bit in the Configuration Register. EEPROM Timebase Divider EEDIV are defined by two registers (EEDIVH and EEDIVL) and must be programmed with a proper value before starting any EEPROM erase/program steps. EEDIV registers must be re-programmed when ever its reference clock is changed. The EEDIV value can be either pre-programmed in the EEDIVHNVR and EEDIVLNVR non-volatile memory registers, (which upon reset will load their contents into the EEDIVH and EEDIVL registers,) or programmed directly by software into the EEDIVH and EEDIVL registers at system initialization. The function of the divider is to provide a constant clock source with a period of 35s (better be within 2ms) to the internal timer and related EEPROM circuits for proper program/erase operations. The recommended frequency range of the reference clock is 250KHz to 32MHz.
1-appA
MC68HC08AZ32 Appendix A: Future EEPROM Registers 391
MOTOROLA
Appendix A: Future EEPROM Registers
EEDIVH and EEDIVL Registers
EEDIVH and EEDIVL are used to store the 11-bit EEDIV value which can be programmed by software at system initialization or during runtime if the EEDIVSECD bit in the EEDIVH is not cleared. The EEDIV value is calculated by the following formula:
EEDIV = INT [ Reference Frequency (Hz) x 35 x 10
-6
+ 0.5 ]
Where the result inside the bracket [ ] is rounded down to the nearest integer value. For example, if the Reference Frequency is 4.9152MHz, the EEDIV value in the above formula will be 172. To examine the timebase output of the divider, the Reference Frequency is divided by the calculated EEDIV value (172), which equals to 28.577KHz in frequency or 34.99s in period. Programming/erasing the EEPROM with an improper EEDIV value may result in data loss and reduce endurance of the EEPROM device.
Address: $FE1A Bit 7 Read: Write: EEDIVSECD x x = Unimplemented x x 6 5 4 3 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8
Reset: EEDIVH-NVR
EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR
Figure 4. EEPROM-2 Divider High Register (EEDIVH)
Address: $FE1B Bit 7 Read: Write: EEDIV7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0
Reset: EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR = Unimplemented
Figure 5. EEPROM-2 Divider Low Register (EEDIVL)
MC68HC08AZ32 392 Appendix A: Future EEPROM Registers
2-appA
MOTOROLA
Appendix A: Future EEPROM Registers EEDIV Non-volatile Registers
EEDIVSECD -- EEPROM Divider Security Disable This bit enables/disables the security feature of the EEDIV registers. When EEDIV security feature is enabled, the state of the registers EEDIVH and EEDIVL are locked (including this EEDIVSECD bit). Also the EEDIVHNVR and EEDIVLNVR non-volatile memory registers are protected from being erased/programmed. 1 = EEDIV security feature disabled 0 = EEDIV security feature enabled EEDIV10-EEDIV0 -- EEPROM timebase prescaler. These prescaler bits store the value of EEDIV which is used as the divisor to derive a timebase of 35s from the selected reference clock source for the EEPROM related internal timer and circuits. EEDIV0-10 are readable at any time. They are writable when EELAT is not set and EEDIVSECD is not cleared.
EEDIV Non-volatile Registers
Address: $FE10 Bit 7 Read: Write: Reset: EEDIVSECD PV PV PV = Unimplemented PV PV 6 5 4 3 2 EEDIV10 PV 1 EEDIV9 PV Bit 0 EEDIV8 PV
Figure 6. EEPROM-2 Divider High Non-volatile Register (EEDIVHNVR)
Address: $FE11 Bit 7 Read: Write: Reset: EEDIV7 PV 6 EEDIV6 PV 5 EEDIV5 PV = Unimplemented 4 EEDIV4 PV 3 EEDIV3 PV 2 EEDIV2 PV 1 EEDIV1 PV Bit 0 EEDIV0 PV
Figure 7. EEPROM-2 Divider Low Non-volatile Register (EEDIVLNVR)
3-appA
MC68HC08AZ32 Appendix A: Future EEPROM Registers 393
MOTOROLA
Appendix A: Future EEPROM Registers
PV = Programmed Value or `1' in the erased state. The EEPROM Divider non-volatile registers (EEDIVHNVR and EEDIVLNVR) store the reset values of the EEDIV0-10 and EEDIVSECD bits which are non-volatile and are not modified by reset. On reset, these two special registers load the EEDIV0-10 and EEDIVSECD bits into the corresponding volatile EEDIV registers (EEDIVH and EEDIVL). The EEDIVHNVR and EEDIVLNVR can be programmed/erased like normal EEPROM bytes if the Divider Security Disable bit (EEDIVSECD) in the EEDIVH is not cleared. The new 11-bit EEDIV value in the non-volatile registers (EEDIVHNVR and EEDIVLNVR) together with the EEPROM Divider Security Disable bit (EEDIVSECD) will only be loaded into the EEDIVH & EEDIVL registers with a system reset.
NOTE:
Once EEDIVSECD in the EEDIVHNVR is programmed to `0' and after a system reset, the EEDIV security feature is permanently enabled because the EEDIVSECD bit in the EEDIVH is always loaded with a `0' thereafter. Once this security feature is armed, erase and program modes are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, great care should be taken before programming a value into the EEDIVHNVR.
MC68HC08AZ32 394 Appendix A: Future EEPROM Registers
4-appA
MOTOROLA
Glossary Glossary
A -- See "accumulator (A)." accumulator (A) -- An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode -- A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus -- The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode -- The way that the CPU determines the operand address for an instruction. The M68HC08 CPU has 16 addressing modes. ALU -- See "arithmetic logic unit (ALU)." arithmetic logic unit (ALU) -- The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous -- Refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate -- The total number of bits transmitted per unit of time. BCD -- See "binary-coded decimal (BCD)." binary -- Relating to the base 2 number system. binary number system -- The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (BCD) -- A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD)
MC68HC08AZ32 MOTOROLA Glossary 395
Glossary
bit -- A binary digit. A bit has a value of either logic 0 or logic 1. branch instruction -- An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module -- A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint -- A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI). break interrupt -- A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus -- A set of wires that transfers logic signals. bus clock -- The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by four. byte -- A set of eight bits. C -- The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). CCR -- See "condition code register." central processor unit (CPU) -- The primary functioning unit of any computer system. The CPU controls the execution of instructions. CGM -- See "clock generator module (CGM)." clear -- To change a bit from logic 1 to logic 0; the opposite of set. clock -- A square wave signal used to synchronize events in a computer.
MC68HC08AZ32 396 Glossary MOTOROLA
Glossary
clock generator module (CGM) -- A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit. comparator -- A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (COP) -- A counter module in the M68HC08 Family that resets the MCU if allowed to overflow. condition code register (CCR) -- An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit -- One bit of a register manipulated by software to control the operation of the module. control unit -- One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. COP -- See "computer operating properly module (COP)." counter clock -- The input clock to the TIM counter. This clock is the output of the TIM prescaler. CPU -- See "central processor unit (CPU)." CPU08 -- The central processor unit of the M68HC08 Family. CPU clock -- The CPU clock is derived from the CGMOUT output from the CGM. The CPU clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by four. CPU cycles -- A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles.
MC68HC08AZ32 MOTOROLA Glossary 397
Glossary
CPU registers -- Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: * * * * * A (8-bit accumulator) H:X (16-bit index register) SP (16-bit stack pointer) PC (16-bit program counter) CCR (condition code register containing the V, H, I, N, Z, and C bits)
CSIC -- customer-specified integrated circuit cycle time -- The period of the operating frequency: tCYC = 1/fOP. decimal number system -- Base 10 numbering system that uses the digits zero through nine. direct memory access module (DMA) -- A M68HC08 Family module that can perform data transfers between any two CPU-addressable locations without CPU intervention. For transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient than CPU interrupts. DMA -- See "direct memory access module (DMA)." DMA service request -- A signal from a peripheral to the DMA module that enables the DMA module to transfer data. duty cycle -- A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage. EEPROM -- Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically reprogrammed. EPROM -- Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception -- An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program.
MC68HC08AZ32 398 Glossary MOTOROLA
Glossary
external interrupt module (IRQ) -- A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch -- To copy data from a memory location into the accumulator. firmware -- Instructions and data programmed into nonvolatile memory. free-running counter -- A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission -- Communication on a channel in which data can be sent and received simultaneously. H -- The upper byte of the 16-bit index register (H:X) in the CPU08. H -- The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction uses the state of the H and C bits to determine the appropriate correction factor. hexadecimal -- Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. high byte -- The most significant eight bits of a word. illegal address -- An address not within the memory map illegal opcode -- A nonexistent opcode. I -- The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) -- A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location. input/output (I/O) -- Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal.
MC68HC08AZ32 MOTOROLA Glossary 399
Glossary
instructions -- Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt -- A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request -- A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine. I/O -- See "input/output (I/0)." IRQ -- See "external interrupt module (IRQ)." jitter -- Short-term signal instability. latch -- A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency -- The time lag between instruction completion and data movement. least significant bit (LSB) -- The rightmost digit of a binary number. logic 1 -- A voltage level approximately equal to the input power voltage (VDD). logic 0 -- A voltage level approximately equal to the ground voltage (VSS). low byte -- The least significant eight bits of a word. low voltage inhibit module (LVI) -- A module in the M68HC08 Family that monitors power supply voltage. LVI -- See "low voltage inhibit module (LVI)." M68HC08 -- A Motorola family of 8-bit MCUs. mark/space -- The logic 1/logic 0 convention used in formatting data in serial communication. mask -- 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon.
MC68HC08AZ32 400 Glossary MOTOROLA
Glossary
mask option -- A optional microcontroller feature that the customer chooses to enable or disable. mask option register (MOR) -- An EPROM location containing bits that enable or disable certain MCU features. MCU -- Microcontroller unit. See "microcontroller." memory location -- Each M68HC08 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus. memory map -- A pictorial representation of all memory locations in a computer system. microcontroller -- Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit. modulo counter -- A counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor ROM -- A section of ROM that can execute commands from a host computer for testing purposes. MOR -- See "mask option register (MOR)." most significant bit (MSB) -- The leftmost digit of a binary number. multiplexer -- A device that can select one of a number of inputs and pass the logic level of that input on to the output. N -- The negative bit in the condition code register of the CPU08. The CPU sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble -- A set of four bits (half of a byte). object code -- The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code.
MC68HC08AZ32 MOTOROLA Glossary 401
Glossary
opcode -- A binary code that instructs the CPU to perform an operation. open-drain -- An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand -- Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator -- A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM -- One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed. overflow -- A quantity that is too large to be contained in one byte or one word. page zero -- The first 256 bytes of memory (addresses $0000-$00FF). parity -- An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. PC -- See "program counter (PC)." peripheral -- A circuit not under direct CPU control. phase-locked loop (PLL) -- A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. PLL -- See "phase-locked loop (PLL)." pointer -- Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity -- The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS. polling -- Periodically reading a status bit to monitor the condition of a peripheral device.
MC68HC08AZ32 402 Glossary MOTOROLA
Glossary
port -- A set of wires for communicating with off-chip devices. prescaler -- A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program -- A set of computer instructions that cause a computer to perform a desired operation or operations. program counter (PC) -- A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use. pull -- An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer. pullup -- A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width -- The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) -- Controlled variation (modulation) of the pulse width of a signal with a constant frequency. push -- An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM address is in the stack pointer. PWM period -- The time required for one complete cycle of a PWM waveform. RAM -- Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit -- A circuit consisting of capacitors and resistors having a defined time constant. read -- To copy the contents of a memory location to the accumulator. register -- A circuit that stores a group of bits. reserved memory location -- A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value. reset -- To force a device to a known condition.
MC68HC08AZ32 MOTOROLA Glossary 403
Glossary
ROM -- Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI -- See "serial communication interface module (SCI)." serial -- Pertaining to sequential transmission over a single line. serial communications interface module (SCI) -- A module in the M68HC08 Family that supports asynchronous communication. serial peripheral interface module (SPI) -- A module in the M68HC08 Family that supports synchronous communication. set -- To change a bit from logic 0 to logic 1; opposite of clear. shift register -- A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed -- A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software -- Instructions and data that control the operation of a microcontroller. software interrupt (SWI) -- An instruction that causes an interrupt and its associated vector fetch. SPI -- See "serial peripheral interface module (SPI)." stack -- A portion of RAM reserved for storage of CPU register contents and subroutine return addresses. stack pointer (SP) -- A 16-bit register in the CPU08 containing the address of the next available storage location on the stack. start bit -- A bit that signals the beginning of an asynchronous serial transmission. status bit -- A register bit that indicates the condition of a device. stop bit -- A bit that signals the end of an asynchronous serial transmission.
MC68HC08AZ32 404 Glossary MOTOROLA
Glossary
subroutine -- A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. synchronous -- Refers to logic circuits and operations that are synchronized by a common reference signal. TIM -- See "timer interface module (TIM)." timer interface module (TIM) -- A module used to relate events in a system to a point in time. timer -- A module used to relate events in a system to a point in time. toggle -- To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode -- Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see "acquisition mode." two's complement -- A means of performing binary subtraction using addition techniques. The most significant bit of a two's complement number indicates the sign of the number (1 indicates negative). The two's complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered -- Utilizes only one register for data; new data overwrites current data. unimplemented memory location -- A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. Executing an opcode at an unimplemented location causes an illegal address reset. V --The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow bit. variable -- A value that changes during the course of program execution. VCO -- See "voltage-controlled oscillator."
MC68HC08AZ32 MOTOROLA Glossary 405
Glossary
vector -- A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (VCO) -- A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform -- A graphical representation in which the amplitude of a wave is plotted against time. wired-OR -- Connection of circuit outputs so that if any output is high, the connection point is high. word -- A set of two bytes (16 bits). write -- The transfer of a byte of data from the CPU to a memory location. X -- The lower byte of the index register (H:X) in the CPU08. Z -- The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00.
MC68HC08AZ32 406 Glossary MOTOROLA
Index Index
A accumulator (A) . . . . . . . . . . . . . . . . . . . . . .53 ACK1 bit (IRQ interrupt request acknowledge bit). . . . . . . . . . . . . . . . . .156, 159-161 ACKK Keyboard acknowledge bit. . . . . . . . . .304 ACQ PBWC . . . . . . . . . . . . . . . . . . . . . . . . .108 ADC analog ground pin (AVSS/VREFL). . . .293 analog power pin (VDDAREF) . . . . . . .293 continuous conversion . . . . . . . . . . . . .291 conversion time . . . . . . . . . . . . . . . . . .290 interrupts . . . . . . . . . . . . . . . . . . . . . . .291 port I/O pins . . . . . . . . . . . . . . . . . . . . .290 voltage conversion . . . . . . . . . . . . . . . .290 voltage in (ADVIN) . . . . . . . . . . . . . . . .293 voltage reference pin (VREFH) . . . . . .293 ADC characteristics. . . . . . . . . . . . . . . . . .382 ADC clock register (ADCLKR). . . . . . . . . .297 ADC data register (ADR). . . . . . . . . . . . . .297 ADC status and control register (ADSCR) 294 ADCO - ADC continuous conversion . . . . . . . . . . . . .295 ADICLK ADC input clock select . . . . . . . . . . . . .298 AIEN - ADC interrupt enable . . . . . . . . . . . . . . . . . .295 arithmetic/logic unit (ALU) . . . . . . . . . . . . . .57 AUTO PBWC . . . . . . . . . . . . . . . . . . . . . . . . .107 B baud rate SCI module . . . . . . . . . . . . . . . . . . . . .195 BCFE C C bit CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SBFCR . . . . . . . . . . . . . . . . . . . . . . . . . 90 BCFE bit (break clear flag enable bit) 90, 160, 180 BCS PCTL . . . . . . . . . . . . . . . . . . . . . . . . . . 106 BIH instruction. . . . . . . . . . . . . . . . . . . . . . 159 BIL instruction . . . . . . . . . . . . . . . . . . . . . . 159 BKF bit (SCI break flag bit) . . . . . . . . . . . . 193 BKPT signal . . . . . . . . . . . . . . . . . . . . . . . 124 block diagram CGM . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 break character . . . . . . . . . . . . . . . . . . . . . 170 break interrupt. . . . . . . . . . . . . . . . . . . . 80, 83 causes . . . . . . . . . . . . . . . . . . . . . . . . . 124 during wait mode . . . . . . . . . . . . . . . . . . 85 effects on COP . . . . . . . . . . . . . . 126, 148 effects on CPU . . . . . . . . . . . . . . . 58, 126 effects on PIT . . . . . . . . . . . . . . . . . . . 282 effects on SPI . . . . . . . . . . . . . . . . . . . 219 effects on TIM . . . . . . . . . . . . . . . 126, 268 effects on TIMA . . . . . . . . . . . . . . . . . . 244 flag protection during . . . . . . . . . . . . . . . 84 break module break address registers (BRKH/L). . . 124, 126-127 break status and control register (BRKSCR) . . . . . . . . . . . . . . . . . 124, 127 break signal. . . . . . . . . . . . . . . . . . . . . . . . 136 BRKA bit (break active bit) . . . . . . . . 124, 127 BRKE bit (break enable bit) . . . . . . . . . . . 127 bus frequency . . . . . . . . . . . . . . . . . . . . . . . 52 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC68HC08AZ32 MOTOROLA Index 407
Index
CCR C bit (carry/borrow flag) . . . . . . . . . . . . .57 H bit (half-carry flag) . . . . . . . . . . . . . . .56 I bit (interrupt mask) . . . . . . . . . . . . . . . .56 N bit (negative flag) . . . . . . . . . . . . . . . .57 V bit (overflow flag) . . . . . . . . . . . . . . . .56 Z bit (zero flag). . . . . . . . . . . . . . . . . . . .57 CGM base clock output (CGMOUT) . . . . . . .103 clock signals. . . . . . . . . . . . . . . . . . . . . .72 CPU interrupt (CGMINT) . . . . . . . . . . .103 crystal oscillator circuit . . . . . . . . . . . . . .95 external connections . . . . . . . . . . . . . .101 interrupts . . . . . . . . . . . . . . . . . . . . . . .111 phase-locked loop (PLL) circuit . . . . . . .95 PLL bandwidth control register (PBWC). . . 97, 107 PLL control register (PCTL) . . . . . . . . .105 PLL programming register (PPG) . . . .109 CGM acquisition/lock time information . . .387 CGM component information . . . . . . . . . .386 CGM operating conditions. . . . . . . . . . . . .386 CGMRCLK signal . . . . . . . . . . . . . . . . . . . .95 CGMRDV signal . . . . . . . . . . . . . . . . . . . . .96 CGMVDV signal . . . . . . . . . . . . . . . . . . . . .96 CGMXCLK signal . . . . . . . . . . . . . . .145-146 duty cycle . . . . . . . . . . . . . . . . . . . . . . .103 CGMXFC pin . . . . . . . . . . . . . . . . . . . . . . . .15 CGND/EVss pin . . . . . . . . . . . . . . . . . . . . .222 CHxF bits (TIM channel interrupt flag bits). . . . 251, 275 CHxIE bits (TIM channel interrupt enable bits) 251, 275 CHxMAX bits (TIM maximum duty cycle bits) . 254, 277 CLI instruction . . . . . . . . . . . . . . . . . . . . . . .56 clock generator module (CGM) . . . . . .92-118 block diagram. . . . . . . . . . . . . . . . . . . . .94 clock start-up from POR . . . . . . . . . . . . . . . . . . . . . . . .73 clock start-up from LVI reset . . . . . . . . . . . .73 COCO/IDMAS Conversions complete/interrupt DMA select . . . . . . . . . . . . . . . . . . . . . . 294 condition code register (CCR). . . . . . . 55, 157 control timing. . . . . . . . . . . . . . . . . . . . . . . 381 COP bit (computer operating properly reset bit) . . . . . . . . . . . . . . . . . . . . . . . . . 145 COP control register (COPCTL) . . . .146-147 COP counter . . . . . . . . . . . . . . .143, 145-148 COP timeout period . . . . . . . . . . . . . 145, 148 COPD MORA . . . . . . . . . . . . . . . . . . . . . . . . . 121 COPRS MORA . . . . . . . . . . . . . . . . . . . . . . . . . 121 CPHA bit (SPI clock phase bit) .206, 221, 224 CPOL bit (SPI clock polarity bit) . . . . . . . . 224 CPU interrupt software . . . . . . . . . . . . . . . . . . . . . 58, 134 CPU interrupt requests SCI. . . . . . . . . . . . . . . . . . . . . . . .178-179 CPU interrupts hardware . . . . . . . . . . . . . . . . . . . . . 80, 82 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 software . . . . . . . . . . . . . . . . . . .80, 82-83 SPI. . . . . . . . . . . . . . . . . . . .215, 218, 226 TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 TIM input capture. . . . . . . . . . . . . . . . . 236 TIM output compare . . . . . . . . . . . . . . 236 TIMA overflow . . . . . . . . . . . . . . . . . . . 243 CPU registers H register . . . . . . . . . . . . . . . . . . . . . . . . 35 stack pointer . . . . . . . . . . . . . . . . . . . . . 35 crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . 101 crystal . . . . . . . . . . . . . . . . . . . . . . . .145-146 crystal amplifier input pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal amplifier output pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . 102 crystal output frequency signal (CGMXCLK) . 103 D DC electrical characteristics . . . . . . . . . . . 380 DMA service requests SPI. . . . . . . . . . . . . . . . . . . . . . . . 215, 226
MC68HC08AZ32 408 Index MOTOROLA
Index
E EEACR EEPROM array configuration register . .48 EECR EEPROM control register. . . . . . . . . . . .46 EENVR EEPROM non-volatile register . . . . . . . .48 EEPROM. . . . . . . . . . . . . . . . . . . . . . . .40-49 block protection . . . . . . . . . . . . . . . . . . .44 configuration . . . . . . . . . . . . . . . . . . . . .44 EEACR. . . . . . . . . . . . . . . . . . . . . . . . . .48 EECR . . . . . . . . . . . . . . . . . . . . . . . . . . .46 EENVR. . . . . . . . . . . . . . . . . . . . . . . . . .48 erasing . . . . . . . . . . . . . . . . . . . . . . . . . .42 programming . . . . . . . . . . . . . . . . . . . . .41 size. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 EEPROM control register (EECR1). .392-393 EESEC MORB . . . . . . . . . . . . . . . . . . . . . . . . .122 electrostatic damage . . . . . . . . . . . . . . . . .308 ELSxA/B bits (TIM edge/level select bits) 252, 276 ENSCI bit (enable SCI bit). . . . . . . . .169, 182 EPROM/OTPROM security . . . . . . . . . . . .120 external crystal . . . . . . . . . . . . . . . . . . . . . .87 external filter capacitor . . . . . . . . . . .102, 115 external filter capacitor pin (CGMXFC) . . .102 external pin reset. . . . . . . . . . . . . . . . . . . . .74 F fBUS (bus frequency). . . . . . . . . . . . . . . . . . .99 FE bit (SCI framing error bit) . . . . . . . . . . .178 FE bit (SCI receiver framing error bit) . . . .192 FEIE bit (SCI framing error interrupt enable bit) 178 FEIE bit (SCI receiver framing error interrupt enable bit). . . . . . . . . . . . . . . . . . . .189 flag protection in break mode . . . . . . . . . . .84 fNOM (nominal center-of-range frequency) . .96 frclk (PLL reference clock frequency) . . . . . .99 fRCLK (PLL reference clock frequency) . . . . .96 fRDV (PLL final reference frequency) . . . . . .96 functional operating range. . . . . . . . . . . . .379
fVCLK (VCO output frequency) . . . . . . . . . . . 96 fVRS (VCO programmed center-of-range frequency) . . . . . . . . . . . . . . .96, 99, 110 H H bit CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I I bit CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I bit (interrupt mask) . . . . . . . . . . . . . 157, 161 I/O port register summary . . . . . . . . . . . . . 308 I/O registers locations . . . . . . . . . . . . . . . . . . . . . . . . 24 IAB (internal address bus) . . . . . . . . . . . . 124 IBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 79 IDLE bit (SCI receiver idle bit). . . . . . 178, 190 idle character . . . . . . . . . . . . . . . . . . . . . . 171 ILAD SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ILIE bit (SCI idle line interrupt enable bit) 178, 186 ILOP SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ILOP bit (illegal opcode reset bit) . . . . . . . . 90 ILTY bit (SCI idle line type bit) . . . . . . . . . 183 IMASK1 bit (IRQ interrupt mask bit) . 157, 161 IMASKK Keyboard interrupt mask bit. . . . . . . . . 304 index register (H:X) . . . . . . . . . . . . . . . . 54, 82 input capture . . . . . . . . . . . . . . .236, 261, 278 interrupt external interrupt pin (IRQ) . . . . . . . . . . 15 interrupt status and control register (ISCR) . . 156 interrupts ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 CGM . . . . . . . . . . . . . . . . . . . . . . . . . . 111 msCAN08 . . . . . . . . . . . . . . . . . . . . . . 341 IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . 156 IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 IRQ status and control register (ISCR) . . . 160
MC68HC08AZ32 MOTOROLA Index 409
Index
IRQ/VPP pin . . . . . . . . . . . . . . . . .15, 155, 159 triggering sensitivity . . . . . . . . . . . . . . .156 IRQ1/VPP pin . . . . . . . . . . . . . . . . . . . . . . .147 IRST signal . . . . . . . . . . . . . . . . . . . . . . . . .74 K KB I/O register summary . . . . . . . . . . . . . .301 KBIE4-KBIE0 Keyboard interrupt enable bits . . . . . . .304 keyboard interrupt control register (KBICR). . . 303 Keyboard interrupt enable register (KBIER) . . 304 KEYF Keyboard flag bit . . . . . . . . . . . . . . . . .303 L L (VCO linear range multiplier) . . . . . . . . . .99 literature distribution centers . . . . . . . . . . .417 LOCK PBWC . . . . . . . . . . . . . . . . . . . . . . . . .107 LOOPS bit (SCI loop mode select bit). . . .182 LVI SRSR . . . . . . . . . . . . . . . . . . . . . . . . . . .90 LVI module . . . . . . . . . . . . . . . . . . . . . . . .153 LVI status register (LVISR) . . . . . . . .150, 152 LVI trip voltage . . . . . . . . . . . . . . . . . . . . .149 LVIOUT bit (LVI output bit) . . . . . . . .150, 152 LVIPWR MORA . . . . . . . . . . . . . . . . . . . . . . . . .120 LVIPWR bit (LVI power enable bit) . . . . . .153 LVIRST MORA . . . . . . . . . . . . . . . . . . . . . . . . .120 LVIRST bit ( LVI reset bit) . . . . . . . . . . . . .150 LVIRST bit (LVI reset enable bit). . . . . . . .153 M M bit (SCI mode (character length) bit) . . 168, 170, 182 mask option register A (MORA) . . . . . . . . . . . . . . . .120 register B (MORB) . . . . . . . . . . . . . . . .122 mask option register (MOR) . . . . . . . 148, 151 maximum ratings. . . . . . . . . . . . . . . . . . . . 378 memory characterisitcs . . . . . . . . . . . . . . . 388 memory map msCAN08 . . . . . . . . . . . . . . . . . . . . . . 354 MODE1 bit (IRQ edge/level select bit) . . 156, 159, 161 MODEK Keyboard triggering sensitivity bit . . . . 304 MODF bit (SPI mode fault bit). . . . . . . . . . 227 monitor commands IREAD . . . . . . . . . . . . . . . . . . . . . . . . . 138 IWRITE . . . . . . . . . . . . . . . . . . . . . . . . 138 READ. . . . . . . . . . . . . . . . . . . . . . . . . . 137 READSP . . . . . . . . . . . . . . . . . . . . . . . 139 RUN. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . 137 monitor mode . . . . . . . . . . . . . . . . . . 126, 147 alternate vector addresses . . . . . . . . . 134 baud rate . . . . . . . . . . . . . . . . . . . . . . . 132 commands . . . . . . . . . . . . . . . . . . . . . . 132 echoing . . . . . . . . . . . . . . . . . . . . . . . . 136 EPROM/OTPROM programming . . . . 132 monitor ROM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MORA COP disable bit (COPD) . . . . . . . . . . . 121 COP rate select (COPRS) . . . . . . . . . . 121 LVI power enable bit (LVIPWR). . . . . . 120 LVI reset enable bit (LVIRST) . . . . . . . 120 ROM security bit (SEC) . . . . . . . . . . . . 120 short stop recovery bit (SSREC) . . . . . 121 STOP enable bit (STOP) . . . . . . . . . . . 121 MORB EEPROM security enable bit (EESEC)122 msCAN08 bus timing register 0 (CBTR0) . . . . . . . 364 bus timing register 1 (CBTR1) . . . . . . . 365 clock system . . . . . . . . . . . . . . . . . . . . 351 control register structure . . . . . . . . . . . 360 CPU WAIT mode . . . . . . . . . . . . . . . . . 350 Data length register (DLR). . . . . . . . . . 358 Data segment registers (DSRn) . . . . . 358
MC68HC08AZ32 410 Index MOTOROLA
Index
external pins. . . . . . . . . . . . . . . . . . . . .334 Identifier Acceptance Control Register (CIDAC) . . . . . . . . . . . . . . . . . . . . .372 identifier acceptance filter . . . . . . . . . .340 Identifier Acceptance Registers (CIDAR0-3) . . . . . . . . . . . . . . . .374 Identifier Mask Registers (CIDMR0-3) .375 identifier registers (IDRn) . . . . . . . . . . .356 internal sleep mode . . . . . . . . . . . . . . .348 interrupt acknowledge . . . . . . . . . . . . .344 interrupt vectors . . . . . . . . . . . . . . . . . .344 interrupts . . . . . . . . . . . . . . . . . . . . . . .341 memory map . . . . . . . . . . . . . . . . . . . .354 message buffer organization . . . . . . . .338 message buffer outline. . . . . . . . . . . . .355 message storage . . . . . . . . . . . . . . . . .335 module control register (CMCR0) . . . .361 module control register (CMCR1) . . . .363 programmable wake-up function . . . . .350 Receive Error Counter (CRXERR). . . .373 receive structures. . . . . . . . . . . . . . . . .336 receiver flag register (CRFLG). . . . . . .366 receiver interrupt enable register (CRIER). 369 Transmit buffer priority registers (TBPR) . . 359 Transmit Error Counter (CTXERR) . . .374 transmit structures . . . . . . . . . . . . . . . .339 Transmitter Control Register (CTCR) .371 Transmitter Flag Register (CTFLG) . . .370 MSxA/B bits (TIM mode select bits) 252, 254, 275, 278 N N bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 NEIE bit (SCI noise error interrupt enable bit) . 178, 191 NEIE bit (SCI receiver noise error interrupt enable bit). . . . . . . . . . . . . . . . . . . . . .188 NF bit (SCI noise flag bit) . . . . . . . . .178, 191
O OR bit (SCI receiver overrun bit). . . . 178, 191 ordering information literature distribution centers . . . . . . . . 417 Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . 418 Web server . . . . . . . . . . . . . . . . . . . . . 418 Web site. . . . . . . . . . . . . . . . . . . . . . . . 418 ORIE bit (SCI overrun interrupt enable bit) . . . 178 ORIE bit (SCI receiver overrun interrupt enable bit) . . . . . . . . . . . . . . . . . . . . . 188 OSC1 pin . . . . . . . . . . . . . . . . . . . . . . 15, 102 OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 15 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 146 oscillator enable signal (SIMOSCEN) . . . . 103 oscillator pins OSC1. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output compare . . . . . . . . . . . . .236, 261, 278 buffered . . . . . . . . . . . . . . . . . . . . 237, 262 unbuffered . . . . . . . . . . . . . . . . . . 236, 261 OVRF bit (SPI overflow bit). . . . . . . . . . . . 227 P page zero . . . . . . . . . . . . . . . . . . . . . . . . . . 55 parity SCI module . . . . . . . . . . . . . . . . . 178, 181 PBWC acquisition mode bit (ACQ) . . . . . . . . . 108 automatic bandwidth control bit (AUTO) . . 107 crystal loss detect bit (XLD). . . . . . . . . 108 lock indicator bit (LOCK) . . . . . . . . . . . 107 PCTL base clock select bit (BCS) . . . . . . . . . 106 PLL interrupt enable bit (PLLIE) . . . . . 105 PLL interrupt flag bit (PLLF) PLLF PCTL105 PLL on bit (PLLON) . . . . . . . . . . . . . . . 106 PE bit (SCI parity error bit) . . . . . . . . . . . . 178 PE bit (SCI receiver parity error bit) . . . . . 192 PEIE bit (SCI parity error interrupt enable bit) 178
MC68HC08AZ32 MOTOROLA Index 411
Index
PEIE bit (SCI receiver parity error interrupt enable bit). . . . . . . . . . . . . . . . . . . . . .189 PEN bit (SCI parity enable bit) . . . . . . . . .183 phase-locked loop (PLL) . . . . . . . . . . .95-101 acquisition mode . . . . . . . . . . .95, 97, 114 acquisition time . . . . . . . . . . . . . . . . . .114 automatic bandwidth mode . . . . . . . . . .97 lock detector. . . . . . . . . . . . . . . . . . . . . .96 loop filter . . . . . . . . . . . . . . . . . . . . . . . .96 manual bandwidth mode . . . . . . . . . . .107 phase detector . . . . . . . . . . . . . . . . . . . .96 programming . . . . . . . . . . . . . . . . . . . . .99 tracking mode . . . . . . . . . . . . . . . . .95, 97 voltage-controlled oscillator (VCO) . . . .97 PIE bit (PIT overflow interrupt enable bit) .284 PIN SRSR . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PIN bit set timing . . . . . . . . . . . . . . . . . . . . . . . .74 PIN bit (external reset bit) . . . . . . . . . . . . . .90 PIT counter . . . . . . . . . . . . . . . . . . . .280, 282 PLL analog power pin (VDDA). . . . . . . . . . .103 PLLIE PCTL . . . . . . . . . . . . . . . . . . . . . . . . . .105 PLLON PCTL . . . . . . . . . . . . . . . . . . . . . . . . . .106 POF bit (PIT overflow flag bit) . . . . . . . . . .284 POR SRSR . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PORRST signal . . . . . . . . . . . . . . . . . . . . . .79 port A. . . . . . . . . . . . . . . . . . . . . .16, 309-310 data direction register A (DDRA) . . . . .309 I/O Circuit . . . . . . . . . . . . . . . . . . . . . . .310 pin functions. . . . . . . . . . . . . . . . . . . . .310 port A data register (PTA) . . . . . . . . . .309 port B. . . . . . . . . . . . . . . . . . . . . .16, 311-313 data direction register B (DDRB) . . . . .312 I/O circuit . . . . . . . . . . . . . . . . . . . . . . .312 pin functions. . . . . . . . . . . . . . . . . . . . .313 port B data register (PTB) . . . . . . . . . .311 port C. . . . . . . . . . . . . . . . . . . . . .16, 314-316 data direction register C (DDRC) . . . . .315 I/O circuit . . . . . . . . . . . . . . . . . . . . . . .316 pin functions . . . . . . . . . . . . . . . . . . . . 316 port C data register (PTC) . . . . . . . . . . 314 port D . . . . . . . . . . . . . . . . . . . . .16, 317-319 data direction register D (DDRD). . . . . 318 I/O circuit . . . . . . . . . . . . . . . . . . . . . . . 319 pin functions . . . . . . . . . . . . . . . . . . . . 319 port D data register (PTD) . . . . . . . . . . 317 port E . . . . . . . . . . . . . . . . . . . . .16, 320-322 data direction register E (DDRE) . . . . . 322 I/O circuit . . . . . . . . . . . . . . . . . . . . . . . 323 pin functions . . . . . . . . . . . . . . . . . . . . 323 port E data register (PTE) . . . . . . . . . . 320 port F. . . . . . . . . . . . . . . . . . . . . .16, 324-326 data direction register F (DDRF) . . . . . 325 I/O circuit . . . . . . . . . . . . . . . . . . . . . . . 326 pin functions . . . . . . . . . . . . . . . . . . . . 326 port F data register (PTF) . . . . . . . . . . 324 port G . . . . . . . . . . . . . . . . . . . . .17, 327, 329 data direction register G (DDRG) . . . . 327 I/O circuit . . . . . . . . . . . . . . . . . . . . . . . 328 port G data register (PTG). . . . . . . . . . 327 port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data direction register H (DDRH). . . . . 329 I/O circuit . . . . . . . . . . . . . . . . . . . . . . . 330 port H data register (PTH) . . . . . . . . . . 329 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . 14 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PPG multiplier select bits(MUL[7 4])109 VCO range select bits (VRS[7:4]) . . . . 110 program counter (PC) . . . . . . . . .55, 126, 159 programmable interrupt timer status and control register (PSC) . . . . 283 programmable interrupt timer (PIT) counter modulo registers (PMODH/L) . 286 counter registers (PCNTH:PCNTL) . . . 285 protocol violation protection . . . . . . . . . . . 346 PRST bit (PIT reset bit). . . . . . . . . . . . . . . 284 PS[2:0] bits (TIM prescaler select bits) . . 233, 248, 272 PSHH instruction. . . . . . . . . . . . . . . . . . . . . 56
MC68HC08AZ32 412 Index MOTOROLA
Index
PSTOP bit (PIT stop bit) . . . . . . . . . . . . . .284 PTY bit (SCI parity bit). . . . . . . . . . . . . . . .183 PULH instruction . . . . . . . . . . . . . . . . . . . . .56 pulse-width modulation (PWM) . . . . . . . . .262 duty cycle . . .239, 242, 254, 263, 266, 277 initialization . . . . . . . . . . . . . . . . .241, 265 R R8 bit (SCI received bit 8) . . . . . . . . . . . . .188 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .35-36 size. . . . . . . . . . . . . . . . . . . . . . . . . .10, 23 stack RAM . . . . . . . . . . . . . . . . . . . . . . .55 RE bit (SCI receiver enable bit). . . . . . . . .186 reset COP . . . . . . . . . . . . . . . . . . . .77, 143, 148 external . . . . . . . . . . . . . . . . . . . . . . . . .75 external reset pin (RST). . . . . . . . . . . . .15 illegal address . . . . . . . . . . . . . . . . .78, 90 illegal opcode . . . . . . . . . . . . . . . . . .78, 90 internal . . . . . . . . . . . . . . . . . . . . . . . . .146 low-voltage inhibit (LVI) . . . . . . . . . . . . .78 power-on . . . . . . . . . . . . . . . . . . . .76, 146 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 security. . . . . . . . . . . . . . . . . . . . . . . . . .37 size. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RPF bit (SCI reception in progress flag bit) . . . 193 RST pin . . . . . . . . . . . . . . . . . . . . . . . . . . .145 during POR timeout . . . . . . . . . . . . . . . .73 RTI instruction . . . . . . . . . . . . . . . .56, 58, 124 RWU bit (SCI receiver wake-up bit) . . . . .187 S SBFCR break clear flag enable bit (BCFE). . . . .90 SBK bit (SCI send break bit) . . . . . . .170, 187 SBSR SIM break STOP/WAIT statur bit (SBSW) . 88 SBSW SBSR . . . . . . . . . . . . . . . . . . . . . . . . . . .88 SCP1-SCP0 bits (SCI baud rate prescaler bits). . . . . . . . . . . . . . . . . . . . . . . . .194
SCRF bit (SCI receiver full bit) . . . . . . . . . 190 SCRIE bit (SCI receiver interrupt enable bit) . 178 SCTE bit (SCI transmitter empty bit) 169, 171, 182, 185, 190 SCTIE bit (SCI transmitter interrupt enable bit) 169, 171, 185 serial communications interface module (SCI) baud rate . . . . . . . . . . . . . . . . . . . . . . . 164 baud rate register (SCBR) . . . . . . . . . . 194 character format . . . . . . . . . . . . . . . . . 184 control register 1 (SCC1). . .168-170, 181 control register 2 (SCC2). . .169-170, 184 control register 3 (SCC3). . . . . . . 168, 187 data register (SCDR) . . . . . . . . . . 169, 194 error conditions . . . . . . . . . . . . . . . . . . 178 framing error . . . . . . . . . . . . . . . . 177, 192 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . 180 noise error . . . . . . . . . . . . . . . . . . . . . . 191 overrun error . . . . . . . . . . . . . . . . . . . . 188 parity error . . . . . . . . . . . . . . . . . . . . . . 178 status register 1 (SCS1) . . . . . . . 169, 189 status register 2 (SCS2) . . . . . . . . . . . 193 serial peripheral interface module (SPI) baud rate . . . . . . . . . . . . . . . . . . . . . . . 226 control register (SPCR) . . . . . . . . . . . . 223 data register (SPDR) . . . . . . . . . . . . . . 229 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . 220 in stop mode . . . . . . . . . . . . . . . . . . . . 218 mode fault error . . . . . . . . . . . . . . . . . . 227 overflow error. . . . . . . . . . . . . . . . . . . . 227 slave select pin . . . . . . . . . . . . . . . . . . 226 status and control register (SPSCR) . . 226 SIM counter power-on reset. . . . . . . . . . . . . . . . . . . . 79 reset states . . . . . . . . . . . . . . . . . . . . . . 79 stop mode recovery . . . . . . . . . . . . . . . . 79 SIMOSCEN signal . . . . . . . . . . . . . . . . . . . 95 SPE bit (SPI enable bit) . . . . . . . . . . . . . . 225 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . 383 SPMSTR bit (SPI master mode bit) . 220, 224 SPR1[1:0] bits (SPI baud rate select bits). 228 SPRF bit (SPI receiver full bit) . . . . . . . . . 226
MC68HC08AZ32 MOTOROLA Index 413
Index
SPRIE bit (SPI receiver interrupt enable bit) . . 223 SPTE bit (SPI transmitter empty bit) . . . . .227 SPTIE bit (SPI transmitter interrupt enable bit) 225 SPWOM bit (SPI wired-OR mode bit)220, 224 SRSR computer operating properly reset bit (COP) . . . . . . . . . . . . . . . . . . . . .90 external reset bit (PIN) . . . . . . . . . . . . . .90 illegal address reset bit (ILAD). . . . . . . .90 illegal opcode reset bit (ILOP) . . . . . . . .90 low-voltage inhibit reset bit (LVI) . . . . . .90 power-on reset bit (POR) . . . . . . . . . . . .89 SSREC MORA . . . . . . . . . . . . . . . . . . . . . . . . .121 stack pointer . . . . . . . . . . . . . . . . . . . . . . . .35 stack pointer (SP) . . . . . . . . . . . . . . . . . . . .54 stack RAM . . . . . . . . . . . . . . . . . . . . . . .35, 55 start bit. . . . . . . . . . . . . . . . . . . . . . . .136, 169 SCI data . . . . . . . . . . . . . . . . . . . . . . . .183 stop bit. . . . . . . . . . . . . . . . . . . . . . . . . . . .169 SCI data . . . . . . . . . . . . . . . . . . . .178, 182 STOP bit (STOP enable bit) . . . . . . . . . . .148 STOP instruction 87, 112, 129, 146, 148, 153, 179, 218, 281 STOP mode. . . . . . . . . . . . . . . . . . . . . . . .292 entry timing . . . . . . . . . . . . . . . . . . . . . .87 recovery from interrupt break. . . . . . . . .87 stop mode . . . . . . . . .129, 145, 153, 193, 281 recovery time . . . . . . . . . . . . . . . . . . . . .73 SWI instruction . . . . . . . . . . .58, 82, 126, 134 system inegration module (SIM) STOP mode . . . . . . . . . . . . . . . . . . . . . .86 system integration module (SIM). . . . . .70-90 break flag control register (SBFCR). . . .90 break status register (SBSR) . . . . . . . . .88 exception control . . . . . . . . . . . . . . . . . .80 reset status register (SRSR) . . . . .89, 145 SIM counter . . . . . . . . . . . . . .79, 145-146 WAIT mode . . . . . . . . . . . . . . . . . . . . . .85 T T8 bit (SCI transmitted bit 8) . . . . . . . . . . . 188 T8 bit (transmitted SCI bit 8) . . . . . . . . . . . 168 TCIE bit (SCI transmission complete interrupt enable bit) . . . . . . . . . . . . . . . . . . . 185 TE bit (SCI transmitter enable bit). . . . . . . 186 TE bit (transmitter enable bit) . . . . . . . . . . 169 thermal characteristics . . . . . . . . . . . . . . . 379 TIMA counter . . . . . . . . . . . . . . . . . . . . . . 244 timer interface module (TIM) . . . . . . . . . ??-278 channel registers (TCH0H/L-TCH3H/L) . . 278 timer interface module (TIMA) channel registers (TACH0H/L-TACH3H/L) 254 channel status and control registers (TASC0-TASC3) . . . . . . . . . . . 250 clock input pin (PTD3/TACLK). . . . . . . 245 counter modulo registers (TAMODH:TAMODL) . . . . . . . . 249 counter registers (TACNTH/L). . .248-249 prescaler . . . . . . . . . . . . . . . . . . . . . . . 233 status and control register (TASC) . . . 246 timer interface module (TIMB) channel registers (TBCH0H/L-TBCH3H/L) 278 channel status and control registers (TBSC0-TBSC1) . . . . . . . . . . . 274 clock input pin (PTD3/TBCLK). . . . . . . 269 clock input pin (PTD4/TBCLK). . . . . . . 259 counter modulo registers (TBMODH/L) . . . 273 counter modulo registers (TBMODH:TBMODL) . . . . . . . . . . . . . . . . . . . 273 counter registers (TBCNTH/L). . .272-273 counter registers (TBCNTH:TBCNTL). 272 status and control register (TBSC) . . . . . . . 270-271 timer module characteristics . . . . . . . . . . . 388 TOF bit (TIM overflow flag bit) . . . . . 247, 271 TOIE bit (TIM overflow interrupt enable bit) . . 247, 271 TOVx bits (TIM toggle on overflow bits) . 253,
MC68HC08AZ32 414 Index MOTOROLA
Index
277 TRST bit (TIM reset bit). . . . . . .247, 252, 272 TSTOP bit (TIM stop bit) . . . . . .247, 252, 271 TXINV bit . . . . . . . . . . . . . . . . . . . . . . . . . .182 TXINV bit (SCI transmit inversion bit)171, 182 U user vectors addresses . . . . . . . . . . . . . . . . . . . . . . .32 V V bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 VDD pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 VRS[7:4] PPG . . . . . . . . . . . . . . . . . . . . . . . . . . .110 VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 W WAIT instruction 85, 112, 129, 148, 153, 179, 218, 243, 267, 281 WAIT mode . . . . . . . . . . . . . . . . . . . .112, 292 wait mode 129, 148, 153, 179, 218, 243, 267, 281 WAKE bit (SCI wake-up condition bit). . . .183 Web server . . . . . . . . . . . . . . . . . . . . . . . .418 Web site . . . . . . . . . . . . . . . . . . . . . . . . . .418 X XLD PBWC . . . . . . . . . . . . . . . . . . . . . . . . .108 Z Z bit CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
MC68HC08AZ32 MOTOROLA Index 415
Index
MC68HC08AZ32 416 Index MOTOROLA
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MC68HC08AZ32 MOTOROLA Literature Updates 417
Literature Updates
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MC68HC08AZ32 418 Literature Updates MOTOROLA
MC68HC08AZ32 TECHNICAL DATA CUSTOMER RESPONSE SURVEY To make M68HC08 documentation as clear, complete, and easy to use as possible, we need your comments. Please complete this form and return it by mail, or FAX it to 512-891-3236. 1. How do you rate the quality of this document? High Organization Readability Accuracy Figures Comments: Low Tables Table of contents Page size/binding Overall impression High Low
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